Layout extracted Parasitics affecting the functionality

[Yogi_bhandari]

Hello all,

I am trying to build a segmented R2R Dac and am curious what all parasitic can kill me. I know pad interconnect resistance, different metal line resistances, contact resistances by their very random nature will show up as mismatch among different resistors in the ladder, thus leading to non linearity.
I am interested in "loosely" quantifying the dependence.

What are your comments?

 

[timof]

Metal interconnects parasitics do not have "very random nature".

There is some randomness, but many random things are correlated with each other.

You should pay attention to parasitic resistances of metal lines and vias, for R2R DAC design.
The best way is to do a layout "correct by construction".
The second best way approach is to do the layout/LVS/DRC/parasitic extraction, then analyze parasitics (via electrical characterization) - to make sure that design resistors remain matched, in post-layout netlist.
Identify the root causes of the mismatch, and eliminate them.

Ideally, you want to match not only parasitic resistances, but also their contributions by layer - since different layers (M1, M2, etc.) are not correlated, so you may get a mismatch from global process variations.