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Layout DC compiler , Encounter , Virtuoso connected to each other

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eng_ahmed_osama

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First Hey All

I have done a design in it's schematic and layout and get the area and write lef file to presented to dc compiler to integrate with encounter layout , My question is about the timing of this design how to present time to dc compiler and encounter to make STA analysis to this new lef file

Second

how to make post place and route simulation ??

Thanks
 

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