layout beginner need help

[eng_ema]

Hi everybody,

i am a beginner in the analog layout field and i want to know the rules i should follow to enhance my layout and reduce the damage possibility
i don't mean the design rules (DRC) , i mean the restrictions to reduce failure mechanism
so i will appreciate any help

thanks alot

 

[erikl]

... restrictions to reduce failure mechanism

Generally: Extend the design rules' limitations wrt. min. width and spacing.

Especially:

• Always use multiple contacts and vias
• Extend the coverage of contacts and vias
• Use more substrate/well taps than required
• Use wider metal than required for current density resp. electro migration prevention

Of course you always have to trade yield/reliability for real estate usage = cost.

For more info, you could g00gle for "semiconductor reliability enhancement" or "semiconductor yield enhancement".