layout area of a circuit in Ledit and Virtuoso

[electronics20]

Dear scholars
Is there any difference between a layout area of a circuit in Ledit and in Virtuoso? Consider a Latch with 12 transistors in TSMC 0.18um.
Thanks in advance

 

[dick_freebird]

If you can assume identical foundry, implementation of rules
decks (and following of, in layout) and artisan skill, then
you can predict equality of outcome. But there are a lot of
fingers in various pies, between foundry, tools vendor, CAD
librarian and layout that could add discrepancies.

Now, if you let the tools auto-place and just pack to rules
based on different initial guesses, the tool itself might have
more influence.

But if I started from a schematic and a blank layout, and
hand placed everything according to my best guesses, the
tool selection would have no influence. The relative quality
of PDK implementation, and its cross-platform consistency,
might.

 

[electronics20]

Many thanks for your precise details and exhaustive explanations. That's great. All right.