Layout: Any risk put two w<<L transistor close?

[xun36]

w/l transistor

Hi,

I have two or more transistors with W=0.5 L=50. I want to put them in the layout one by one aligned by their length. But in this case the the channels of two MOS gets very close. Is there any risk? Like the gate will reverse the Nwell to Ptype and make a short inbetween the two N channel?

Thanks.

 

[aznsj]

I think it depends on which DRC rule you are used.

 

[xun36]

So you mean if DRC is clean, it should work...?

I think it depends on which DRC rule you are used.

 

[shitansh]

hi,

What i am suggesting is if you want to kept two transistor close alinged by chennel lenght then you have to arrange like infrunt of source of one transistor there should be drain of another transistor.

Advantage of that is if both transistors are simultaneously on then current direction in both Txs are in reverse direciton so possiblity is less.

Let me know others suggesion on this.

 

[sreevyas]

could i know what do you mean by L and W
width should be always greater than length
i could not understand

__sree

 

[keiichi451]

MOS W is not required to be greater than L.

One example of a large channel length is if you want to create a simple RC delay by using a MOS in triode/linear region. To create a increase the R, you would make the channel length longer.

 

[snafflekid]

If the design rules say it is okay, then it is okay.

There is a field implant in all the surface of the nwell. This makes it very hard to invert the areas between transistors and create a channel between two adjacent transistors.

I will add, if you operate one transistor with too high voltage or break it down, it will affect any transistor next to it.

 

[sreevyas]

I saw some where Design rule say the distance between two transistors at least 3 to 4L

__sree

 

[vpabba]

The DRC it self say that it will work with out any problem, but in general in industry all are not going with exact DRC rules means that they put the spacing between them more than as specified in DM to get better quality and better yield. but in this case it not possible in newer technologies since the technology is restricted by the poly pitches i.e. u have to place the transistors on that specified locations only

 

[rfsystem]

As posted before there is a field implant in between. If there is a poly wire above field oxide but between the two long (L>>W) MOS it could create a channel. The device is the parasitic field oxide MOS which has a threshold voltage typical higher than the maximum supply voltage. But below the threshold voltage the subthreshold current could impact very low current diffusions which require high accurcay. So place a stop P+ diffusion which is connected to NWELL.

High voltage IC's are much more critical where some devices have operating voltages above the low voltage field oxide thresholds.