arikp
Newbie level 4
I am trying to divide a 100Mhz input CPLD clk by 4 and take out this 25Mhz to another CPLD pin.
I need the best Jitter from a MACHXO2-256 device.
I am aware of the fact that placing my counter close to the IOs will help and adding FF on the counter's output will also help.
I need a working example how to locate the following group physically in the floorplan as close as possible together withing the CPLD :
Group contains : input clk pin , output pin , 2 counter FFs , one optional sampling FF after the final counter FF.
Thank you for any relevant verilog code.
I need the best Jitter from a MACHXO2-256 device.
I am aware of the fact that placing my counter close to the IOs will help and adding FF on the counter's output will also help.
I need a working example how to locate the following group physically in the floorplan as close as possible together withing the CPLD :
Group contains : input clk pin , output pin , 2 counter FFs , one optional sampling FF after the final counter FF.
Thank you for any relevant verilog code.