Continue to Site

Welcome to

Welcome to our site! is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Lattice CPLD ispLSI2096E-100LT128

Not open for further replies.


Junior Member level 1
Mar 30, 2002
Reaction score
Trophy points
Activity points

Hi guys,

I design this CPLD (ispLSI2096E-100LT128) for the first time, I'm looking for who had experience with this chip and could help me to solve some trouble. Now I'm stuck ith 'CLOCK' signal, I received message like that : "33226 ERROR : clock 'CLOCK' locked to pin 'Y0' does not support fast clock inversion " (It happened in when I start "Fit Design" in "ispLEVER Project Navigator" ). Although all signals in my design operate at posedge clock.

Please kindly help me !!!

lattice error that does not support high speed


Lattice CPLD architectures have many clock distribution limitations. You first need to study ispLSI2096architecture before you make your design.

Lattice PLDs have clock distribution networks for IO cell clock and GLB clock. You can not use same clock for IO cell and GLB. In that case you need to connect external clock on two external clock pins.

If you want to invert GLB clock you need to use PT clock (see Lattice Data Sheets for architectural descriptions).

If your design does not meet these clock restrictions you need to make redesign for ispLSI2096.

If you use HDL descriptions you need additional directives to specify signal-pin locks, clock signals and signal groups. Without directives compiler often makes errors. Lattice compiler has some bugs. In some cases it cannot fit fitable designs and generates erros.

If you do not need high-speed design you can use IO or Input pin instead of clock pin.

Lattice CPLD architectures have some specific features. If you want to optimaly use Lattice CPLDs you need to optimize your design for Lattice.




I suggest you use the Mach4064 or Mach4128. They are better than the ispLSI2096E-100LT128. Faster and low power.
In mach4000 you can make some logic with the clock pin. But in the isp1000 or isp2000, it will make some trouble.
If you have to use the lsi2096, you should lock the clock to some other common I/O pin.

using cpld as a clock distribution


I have solved this problem. Just free pin clock in contraints editor and let the software choose clock pin.
I thing more about you chip

lattice mach4064


Do you use only Lattice CPLD or also use another vendors cplds? Does Lattice chips have any advantages as compared to Xilinx/Altera?

lattice cpld programming

Hi karabas
Sorry, I have a long time not to come here. I see this post just today.

I use Xilinx and Lattice. Lattice CPLD is cheaper than Xilinx.
To Altera, Lattice use all CMOS technology. But Altera use TTL GPR technology. So Lattice is low power than Altera, and faster than Altera's MAX7000.

Of course, these result are tested by the three vender's lastest product series.--Lattice's ispMACH4000, Altera's MAX7000, Xilinx's CoolrunnerII

Not open for further replies.

Part and Inventory Search

Welcome to