back to back flops (synchronizer) on clk1 with async input at d pin. When async input changes, you may see output change after 2-3 clks. Is this correct?
back to back flops (synchronizer) on clk1 with async input at d pin. When async input changes, you may see output change after 2-3 clks. Is this correct?
For a double sync you should ideally see the output after 2 destination clocks. However, when you move from one clock domain to other, synchornizers make sure that probability of metastability will be reduced to almost 0, but they do not guarantee that data will be sampled in 2 clock cycles. Data may take more time than that.