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Latches and flip flops

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vlsitechnology

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latches and flip flops

In which part of the design we use only latches but not flip flops and why ? What happens if we use latches instead of flip flops in a design...Glitches problem, or analysis problem or delay problem?
 

are latches sensitive to glitches

If we use Latch Glitches problem will occur..

Because Latch is sensitive to glitches on enable pin, whereas flip-flop is immune to
glitches.
 

vlsitechnology said:
In which part of the design we use only latches but not flip flops and why ? What happens if we use latches instead of flip flops in a design...Glitches problem, or analysis problem or delay problem?

In the clock sensitive part of your design you should use flipflop in stead of latch. And it's all depends on your design style and algorithm.
 

One more this is that , Latch is level triggered device while flipflop is edge triggered , so if u use latched instead of flipflop then u will get lot of timing
Voilations
 

It is all dependent on what you want to design and how.
design with latches is more complicated (non overlapping clocking scheme, DFT issues, carefully designing feedback loops etc.) but it can be faster and can be less power hungry.

FF are more straight forward and most companies prefer FF design on their flows. but there is no "correct" way to design.

I generally use flip flops in my designs but had built several circuits that benefited from using latches.

ND.
https://asicdigitaldesign.wordpress.com/
 

Usage of latches :(few pts from my side)
Latches are used in Clock Gater ckt, as all of know a simple basic opn of latch is whenever enable pin is on.it will allow the data what ever present in the i/p.mainly for hold d previos data if enable pin is on.

One more imp place using of latches are:
In DFT, during flush test clock skew btwn two flops are working in two differnt clock domains.due to prop. delay from o/p of one clock domain flop in to i/p to another clock domain flop will cause a data loss and mismatches.... in that time we will overcome this pbm by using Lock-up latches.
 

The good practice , i think is :

flip-flop + logic

avoiding Latch
 

nine8 said:
The good practice , i think is :

flip-flop + logic

avoiding Latch

This is a good rule of thumb for your general design and for going smoothly through your flow and achieving a reliable design ASAP.

BUT it is my personal opinion that if you consider yourself a good designer, you have to learn to design with latches as well. There are times that because of power/latency/etc. issues you want to use latches instead of flops. In these cases you gotta be ready and know what "dirty evil monsters" are waiting for you behind the corner when using latches.

A good designer must know latch based design.

just my two cents,

ND.
https://asicdigitaldesign.wordpress.com/
 

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