I think the base is way overdriven (you need only
about 160uA collector current to bury the load,
but are throwing about +/-1mA at the base).
Look at the transition times on the input source.
I think the dV/dt there may be blowing through
the Cjc and bumping the output. You might add
some shunt C, base to emitter, to help soak up
any overly fast input transitions (with 3.3V logic
and a 20K pullup it's not like you're going to be
caring about RF). But I'd begin with assessing
input stimulus sanity.
Input divider network should ensure that the
reverse voltage applied in the -24V case will
not exceed the reverse Vbe rating of the
transistor. You could knock R10 down to 1-2K
and still work fine. I'd also lower the collector
pullup if you care at all about LH prop delay
or prop delay symmetry, especially if there is
any length of routing or this circuitry feeds
anything with much input capacitance.
For that matter I might think about a "single
gate logic" Schmitt trigger chip in a 3.3V compatible
family, if you can find one. Probably no bigger,
symmetric and controlled drive, likely faster and
no 160uA low-output-state current draw.