chanchg said:
Hello Everyone,
Is is possible to design a Sig-Del ADC(probably switch-cap based) with following specs?
1. I/P Signal Bandwidth = 2.2Mhz
2. Conversion Rate = 8Mhz
3. Linearity = 16 bit
Process 0.13u TSMC or 0.18u TSMC.
Regards,
Chanchal
according to ur spec.
f0=2.2M, fnyquist=4.4M, fc=8M
I try to deduce the require equation:
there is a ideal equation about SNR , OSR and order (N) of SDM.
the increasing bit of a N order SDM with every double of OSR is (N+0.5) bit.
so 16 =< 1+K(N+0.5)
1. if N=3 ===> K>=5 ===> choose K=5 the OSR should at lease 2^5=32
so u will need over sampling clock rate as fs=32*fnyquist= 140.8MHz ,
this spec. will be reflected to ur OP design of the modulator.
the minimal UGB of ur op will be 3*2fs= 844.8MHz.*
it is possible in .18u process. but more good in .13u process
2. if N=4 ===> K=4, OSR=2^4=16,
so u will need over sampling clock rate as fs=16*fnyquist= 70.4MHz
the minimal UGB of ur op will be 3*2fs= 422.4MHz.*
it is possible in .18u process.
there is a assumption above with *, that is the setting behavior of OP in S/H, cause there should exist gain error .
hopes this help u