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Large digital chip: 40k gates/10k registers

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orient

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Hi there,

I am working on large ASIC design with approximately 40k gates, including 10k flop-flops. The design has mostly a single clock, except for some other smaller clock domains (JTAG's TCK, etc).

I have already fully tapeout and tested other digital-on-top ASICs on the same technology (0.18um CMOS), but this time, I am much worried about the clock signal that has to clock these 10k registers. Also, there are some mixed-signal blocks on the same chip, I want to keep my power lines as clean as possible.

The price I am willing to pay is a lot of VDD/GND pads. I can have as much as possible, as long as it remains reasonable. I still need to use a 128-pin package eventually, and a fraction of these pads are already taken.

Does anyone know how I could estimate the number of VDD/GND pads I need to use for a given switching-noise figure?

What worries me too, is that the same design consumes a large chunk of a Cyclone III FPGA device (85% of a EP3C55). But that FPGA device has a huge number of power pads and its package uses flip-chip technology, so the decoupling caps are very close to the chip. Am I heading toward a disaster?

Please, any ideas and comments would be highly appreciated.
 

rca

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some remarks:
1- large 40k?
2- how many scan clocks do you have? or do you ignore the jtag-flops from the scan? If you have only one scan clock domain, your design will synthesis fully synchronously, but your design requires to be simulate with two clock domains.
3- did you share the same power/ground lines between the analog and the digital part, or do have a separate regulator for the digital, to reduce the cross-talk through the power lines between analog to digital and digital to analog ( I don't know, how your analog is sensitive?)
4- basicly you need to estimate the power consumption and the equivalent "resistance" of both part to know how the voltage could be droped.
5- for my concern, I will not worried about a clock tree with 10k flops, no special stuff.
 

orient

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Hi, thanks for the reply! You're totally right, 40k is no big deal. I am way more concerned with the clock tree for the 10k flip-flops indeed.

Let me go over your points:

1. Not so indeed, sorry.

2. I have only one scan clock domain, it should be no big deal I hope.

3. Yes, this is a critical point indeed. To be honest, I haven't decided how to proceed regarding this issue. Ideally they should be separated, but in practice it is not so easy, especially with a digital-on-top design flow. Most of sensitive analog circuits uses 3.3V power supply, so they will be indeed isolated from the digital 1.8V. Perhaps the groud line will be shared on chip. Anyway, many people says to separate the ground between analog and digital, but the thuth is I don't understand how people manage the return-path of fast signals going from one domain to another (if grounds are not connected on-chip). Off chip and come back? Maybe I will post another thread on this issue...

4. Yes, I will do that. Try to figure out the worst-case peak current then determine the number of pads, if I succeed an accurate full chip simulation (using ultrasim). As an alternative, I could make a fake schematic with 10k flops and simulate just that, what do you think?

5. Good to hear that. Thanks.
 

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