Large CMOS inverter ( many inverters in parallel ) driving off-chip capacitive load

[dan11]

I need to design large CMOS inverter (many inverters in parallel) driving large off-chip capacitive load. Do I need to place resistor between NMOS drain and inverter output to limit current to each parallel inverter? Any good references on such a design?

thanks!

 

[dick_freebird]

I'd start with simple time averaged current (@ max rated
freq) and see whether there is any interconnect overstress
that can be calculated. FETs tend to share pretty well. If
I had a per-finger current over about half reliability rating
I'd consider per-finger or maybe per-inverter ballasting.
Try fast corner, max temp for the current and min linewidth
electromigration calculations. As channels get shorter and
lower levels interconnect gets skinnier, it's more possible
to have devices that can't support their own weight, as it
were.

Sometimes (especially on old-school few-levels interconnect,
as is still found in some power IC processes) the ballast can
be a handy crossunder and cost you little in terms of net
area.

 

[dan11]

Thank you! Do you think additional design consideration for placing ballasting resistor might be to limit short circuit current to ground when both nmos and pmos are conducting?

 

[dick_freebird]

That aspect should be handled by phasing the internal high
and low side gate drives for break-before-make.

 

[dan11]

Thank you but I am not sure what you mean by "break-before-make". The large output CMOS inverter is driven by smaller on-chip inverter. So when the input to large CMOS inverter gates is Vdd/2 both nmos and pmos will conduct current to ground.

 

[dick_freebird]

Right. But if you split the taper-chain further back, the
vdd/2 point for each does not have to happen at the
same time.

When you're talking designs like a 10A POL buck's totem
pole, you can't afford current limiting in the power-out,
out-gnd paths and you have to make them quit stepping
on each other, instead. In large output drivers you will
probably have 4-10 stages of taper before the final which
gives you plenty of room to set up some "ballistic" timing
by asymmetric drive. You can also use some strategically
placed feedback and combo logic to run things a little
tighter than a purely W-skew chain might give you /PVT.