Lanuch Verilog-XL error in IC5.0

[benny16]

invalid ncvlog executable

Hi, when i use Verilog-XL sim the schematic, that shown:

SIMULATION OPTION WARNING:
Invalid verilog executable verilog
Please check existance and/or permissions and try again. Relative pathnames are relative to run directly.

Press OK, i can open the verilog-XL window and check CIW-option- license, "virtuoso schematic composer verilog interface" is running.

So, after input the simuli into testhbench.verilog and run "start interactive", another warning is shown:
WARNING: VLOGIF [BADFILE GLOBAL]
user-setable global variable: verilogSimBinary is invalid
relative pathnames are relative to run directory OK/CANCEL aborts simulation.

My installed directory of IC 5.0 is /tools/cds5 and Linux RH7.3

Thanks
Benny

 

[Fom]

invalid nc-verilog executable

I remember Verilog is not included in IC5.0. You need LDV package to run Verilog.

 

[labodhibo]

invalid verilog executable verilog

Fom is right,
You have to have LDV release in place for VerilogXl
NC is the way to go.

Labo

 

[benny16]

verilogsimbinary is invalid

in IC 5, the verilog-XL is only can sim the gate level. I can run it in UNIX, but maybe my PC have different path set.

Regards,
Benny

 

[labodhibo]

verilog-xl verilog 2001

PC?
IC5 is not supported in windows. Only linux.
Labo

 

[OvErFlO]

invalid verilog executable

I had the same problem, I have resolve installing LDV package and set a correct PATH name in bin directory of LDV...