L\eonard0 Spec\trum For ASIC Synthesis

[eda_wiz]

Hi all,
how good is leonardo Spectrum for ASIC Synthesis. I am getting Huge gatecount for a small Logic in spectrum
helppp

tnx

 

[gnomix]

I haven't experience with LS but every time that I have used it I had problems.

The solution can be to use a serious synthesis tool

 

[dspusr]

2003a_RC_9 seems to be (pre-)released.
but can't use lic for 2002e.

 

[haifengyuyun]

is it powerful than DC when synthesis?

maybe it it quick then DC,but how is it effect?

 

[Zerox100]

2003a_RC_9 seems to be (pre-)released.
but can't use lic for 2002e.

A link please?

 

[RTL2GDSII]

This gate count are always confusing.
Different tool has different criteria.

 

[ted]

I have used Leonardo Spectrum now for a year and half for developing for Altera ACEX1K50. I would say, the tool is useful; some features are god others so-and-so. In my particular configuration I used MAX II Plus for the physical layout, while the source code was VHDL. The combination Leonardo and MAX made me to loose track of the physical elements<->VHDL source code completely, so floor planning was a nightmare. I had no problem with space, but speed was a issue, so manual optimization was needed.

In the end I converted to use Quartus II 2.2, and its native VHDL compiler. Now I can see the connection between VHDL and the floor plan much better. Of course, Quartus has a much better "timing closure" floorplanning functionality than MAX II Plus anyway.

What I miss from Leonardo is the "generated schematics" stuff, which I used for block-schematics level documentation. Generated logic however was not that good and the grazy node and net names generated by Leonardo->edif file->MAX was the biggest curse. Somewhat inefficient code generation was not fun either. There the difference was not that big, however.

I would not compare Leonardo against any other system, because the only VHDL -> FPGA compilers I have used are the above mentioned ones. And I decided to get rid of Leonardo Spectrum in favor of Quartus II 2.2

And I had FPGA, not an ASIC as my target. But, I guess, some of the wonderful synthesizing grazyness is valid for Leonardo in all instances. In several cases the logic wasn't pretty ! But my technology dependent libraries were not equal to yours, so the wild gate count might have some connection to the library implementations, too.

Ted