eziggurat
Full Member level 6
rvdk keil
Hi,
I am trying to port UCOS to LPC2103 using the latest code but I still can't get it to work.
I have rewritten my code to turn on LCD backlight with and
without the UCOS. The code without the UCOS just call the
BackLightingOn() and InitPort functions in the main() and this works
fine but I want to be able to get UCOS running. The code below shows a
task been created to turn on the backlight and delay, OSTimeDlyHMSM().
The code suppose contain several tasks but I have reduced to one so I
can figure out how to get UCOS running on the LPC2103 by turning on
the back light but I can't see the problem in the code.
The code for the main code is shown below.
#include "LPC2103.h"
#include "os_cpu.h"
#include "cpu.h"
#include "app_cfg.h"
#include "ucos_ii.h"
#define Fosc 16000000 //Crystal
frequence,10MHz~25MHz£¬should be the same as actual status.
#define Fcclk (Fosc * 3) //System
frequence,should be (1~32)multiples of Fosc,and should be equal or
less than 60MHz.
#define Fpclk (Fcclk / 4) * 1 //VPB clock
frequence , must be 1¡¢2¡¢4 multiples of (Fcclk / 4).
static OS_STK AppTaskStartStk[APP_TASK_START_STK_SIZE];
static void AppTaskStart (void *p_arg);
void tc3 (void){
T3IR = 1; // Clear interrupt flag
OSTimeTick();
FIOPIN1^=0x08; //debugging
VICVectAddr = 0; // Acknowledge Interrupt
}
void StartTicker(void){
T3MR0 = Fpclk/OS_TICKS_PER_SEC-1; // 1mSec = 15000-1 counts at 15
Mhz PCLK
T3MCR = 3; // Interrupt and Reset on MR0
T3TCR = 1; // Timer0 Enable
VICVectAddr0 = (unsigned long)tc3; // set interrupt vector in 0
VICVectCntl0 = 0x20 | VIC_TIMER3; // use it for Timer 0
Interrupt
VICIntEnable = 1<<VIC_TIMER3; // Enable Timer0 Interrupt
}
void BackLightingOn(void){
// BackLightingOnFlag=1;
// BackLightingOnTimer=0;
IOSET=0x04000000;
FIOSET3=0x04;
}
void Initport(void){
IODIR=0x0C81000C;
FIODIR0=0x0C;
FIODIR2=0x81;
FIODIR3=0x0C;
FIOPIN2=0x00;
FIOPIN3=0x00;
FIODIR1=0x08;
FIOPIN1=0x00;
}
void BSP_IntDisAll (void)
{
VICIntEnClr = 0xFFFFFFFFL; /*
Disable ALL interrupts */
}
int main (void){
BSP_IntDisAll(); //disable interrupts
OSInit();
OSTaskCreateExt(AppTaskStart, /* Create
the start task */
(void *)0,
(OS_STK *)&AppTaskStartStk[APP_TASK_START_STK_SIZE
- 1],
APP_TASK_START_PRIO,
APP_TASK_START_PRIO,
(OS_STK *)&AppTaskStartStk[0],
APP_TASK_START_STK_SIZE,
(void *)0,
OS_TASK_OPT_STK_CHK | OS_TASK_OPT_STK_CLR);
OSStart();
return (0);
}
static void AppTaskStart (void *p_arg)
{
(void)p_arg;
OS_CPU_InitExceptVect();
SCS=0x03;
if( WDMOD & 0x04 ){
WDMOD &= ~0x04;
}
StartTicker();
//BSP_Init(); /*
Initialize BSP functions */
Initport(); // Initialise the ports
/* Create application tasks
*/
while (1) { /* Task body,
always written as an infinite loop. */
BackLightingOn(); // Turn Backlight On
OSTimeDlyHMSM(0, 0, 0, 5);
}
}
/*
********************************************************************************\
*************************
* OS_CPU_ExceptHndlr()
*
* Description : Handle any exceptions.
*
* Argument(s) : except_id ARM exception type:
*
* OS_CPU_ARM_EXCEPT_RESET
0x00
* OS_CPU_ARM_EXCEPT_UNDEF_INSTR
0x01
* OS_CPU_ARM_EXCEPT_SWI
0x02
* OS_CPU_ARM_EXCEPT_PREFETCH_ABORT
0x03
* OS_CPU_ARM_EXCEPT_DATA_ABORT
0x04
* OS_CPU_ARM_EXCEPT_ADDR_ABORT
0x05
* OS_CPU_ARM_EXCEPT_IRQ
0x06
* OS_CPU_ARM_EXCEPT_FIQ
0x07
*
* Return(s) : none.
*
* Caller(s) : OS_CPU_ARM_EXCEPT_HANDLER(), which is declared in
os_cpu_a.s.
********************************************************************************\
*************************
*/
void OS_CPU_ExceptHndlr (CPU_INT32U except_id)
{
CPU_FNCT_VOID pfnct;
if (except_id == OS_CPU_ARM_EXCEPT_IRQ) {
pfnct = (CPU_FNCT_VOID)VICVectAddr; /*
Read the interrupt vector from the VIC */
while (pfnct != (CPU_FNCT_VOID)0) { /*
Make sure we don't have a NULL pointer */
(*pfnct)(); /*
Execute the ISR for the interrupting device */
VICVectAddr = 1; /*
Acknowlege the VIC interrupt */
pfnct = (CPU_FNCT_VOID)VICVectAddr; /*
Read the interrupt vector from the VIC */
}
} else {
/*
Infinite loop on other exceptions. */
/*
Should be replaced by other behavior (reboot, etc.) */
while (1) {
;
}
}
}
Added after 46 seconds:
My startup script is shown below.
;/*****************************************************************************/
;/* STARTUP.S: Startup file for Philips LPC2000
*/
;/*****************************************************************************/
;/* <<< Use Configuration Wizard in Context Menu >>>
*/
;/*****************************************************************************/
;/* This file is part of the uVision/ARM development tools.
*/
;/* Copyright (c) 2005-2007 Keil Software. All rights reserved.
*/
;/* This software may only be used under the terms of a valid,
current, */
;/* end user licence from KEIL for a compatible version of KEIL
software */
;/* development tools. Nothing else gives you the right to use this
software. */
;/*****************************************************************************/
;/*
; * The STARTUP.S code is executed after CPU Reset. This file may be
; * translated with the following SET symbols. In uVision these SET
; * symbols are entered under Options - ASM - Define.
; *
; * REMAP: when set the startup code initializes the register MEMMAP
; * which overwrites the settings of the CPU configuration pins. The
; * startup and interrupt vectors are remapped from:
; * 0x00000000 default setting (not remapped)
; * 0x80000000 when EXTMEM_MODE is used
; * 0x40000000 when RAM_MODE is used
; *
; * EXTMEM_MODE: when set the device is configured for code execution
; * from external memory starting at address 0x80000000.
; *
; * RAM_MODE: when set the device is configured for code execution
; * from on-chip RAM starting at address 0x40000000.
; *
; * EXTERNAL_MODE: when set the PIN2SEL values are written that enable
; * the external BUS at startup.
; */
; Standard definitions of Mode bits and Interrupt (I & F) flags in PSRs
Mode_USR EQU 0x10
Mode_FIQ EQU 0x11
Mode_IRQ EQU 0x12
Mode_SVC EQU 0x13
Mode_ABT EQU 0x17
Mode_UND EQU 0x1B
Mode_SYS EQU 0x1F
I_Bit EQU 0x80 ; when I bit is set, IRQ is
disabled
F_Bit EQU 0x40 ; when F bit is set, FIQ is
disabled
;// <h> Stack Configuration (Stack Sizes in Bytes)
;// <o0> Undefined Mode <0x0-0xFFFFFFFF:8>
;// <o1> Supervisor Mode <0x0-0xFFFFFFFF:8>
;// <o2> Abort Mode <0x0-0xFFFFFFFF:8>
;// <o3> Fast Interrupt Mode <0x0-0xFFFFFFFF:8>
;// <o4> Interrupt Mode <0x0-0xFFFFFFFF:8>
;// <o5> User/System Mode <0x0-0xFFFFFFFF:8>
;// </h>
UND_Stack_Size EQU 0x00000000
SVC_Stack_Size EQU 0x00000008
ABT_Stack_Size EQU 0x00000000
FIQ_Stack_Size EQU 0x00000000
IRQ_Stack_Size EQU 0x00000080
USR_Stack_Size EQU 0x00000400
ISR_Stack_Size EQU (UND_Stack_Size + SVC_Stack_Size +
ABT_Stack_Size + \
FIQ_Stack_Size + IRQ_Stack_Size)
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE USR_Stack_Size
__initial_sp SPACE ISR_Stack_Size
Stack_Top
;// <h> Heap Configuration
;// <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF>
;// </h>
Heap_Size EQU 0x00000000
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
; VPBDIV definitions
VPBDIV EQU 0xE01FC100 ; VPBDIV Address
;// <e> VPBDIV Setup
;// Peripheral Bus Clock Rate
;// <o1.0..1> VPBDIV: VPB Clock
;// <0=> VPB Clock = CPU Clock / 4
;// <1=> VPB Clock = CPU Clock
;// <2=> VPB Clock = CPU Clock / 2
;// <o1.4..5> XCLKDIV: XCLK Pin
;// <0=> XCLK Pin = CPU Clock / 4
;// <1=> XCLK Pin = CPU Clock
;// <2=> XCLK Pin = CPU Clock / 2
;// </e>
VPBDIV_SETUP EQU 0
VPBDIV_Val EQU 0x00000000
; Phase Locked Loop (PLL) definitions
PLL_BASE EQU 0xE01FC080 ; PLL Base Address
PLLCON_OFS EQU 0x00 ; PLL Control Offset
PLLCFG_OFS EQU 0x04 ; PLL Configuration Offset
PLLSTAT_OFS EQU 0x08 ; PLL Status Offset
PLLFEED_OFS EQU 0x0C ; PLL Feed Offset
PLLCON_PLLE EQU (1<<0) ; PLL Enable
PLLCON_PLLC EQU (1<<1) ; PLL Connect
PLLCFG_MSEL EQU (0x1F<<0) ; PLL Multiplier
PLLCFG_PSEL EQU (0x03<<5) ; PLL Divider
PLLSTAT_PLOCK EQU (1<<10) ; PLL Lock Status
;// <e> PLL Setup
;// <o1.0..4> MSEL: PLL Multiplier Selection
;// <1-32><#-1>
;// M Value
;// <o1.5..6> PSEL: PLL Divider Selection
;// <0=> 1 <1=> 2 <2=> 4 <3=> 8
;// P Value
;// </e>
PLL_SETUP EQU 1
PLLCFG_Val EQU 0x00000024
; Memory Accelerator Module (MAM) definitions
MAM_BASE EQU 0xE01FC000 ; MAM Base Address
MAMCR_OFS EQU 0x00 ; MAM Control Offset
MAMTIM_OFS EQU 0x04 ; MAM Timing Offset
;// <e> MAM Setup
;// <o1.0..1> MAM Control
;// <0=> Disabled
;// <1=> Partially Enabled
;// <2=> Fully Enabled
;// Mode
;// <o2.0..2> MAM Timing
;// <0=> Reserved <1=> 1 <2=> 2 <3=> 3
;// <4=> 4 <5=> 5 <6=> 6 <7=> 7
;// Fetch Cycles
;// </e>
MAM_SETUP EQU 1
MAMCR_Val EQU 0x00000002
MAMTIM_Val EQU 0x00000004
; External Memory Controller (EMC) definitions
EMC_BASE EQU 0xFFE00000 ; EMC Base Address
BCFG0_OFS EQU 0x00 ; BCFG0 Offset
BCFG1_OFS EQU 0x04 ; BCFG1 Offset
BCFG2_OFS EQU 0x08 ; BCFG2 Offset
BCFG3_OFS EQU 0x0C ; BCFG3 Offset
;// <e> External Memory Controller (EMC)
EMC_SETUP EQU 0
;// <e> Bank Configuration 0 (BCFG0)
;// <o1.0..3> IDCY: Idle Cycles <0-15>
;// <o1.5..9> WST1: Wait States 1 <0-31>
;// <o1.11..15> WST2: Wait States 2 <0-31>
;// <o1.10> RBLE: Read Byte Lane Enable
;// <o1.26> WP: Write Protect
;// <o1.27> BM: Burst ROM
;// <o1.28..29> MW: Memory Width <0=> 8-bit <1=> 16-bit
;// <2=> 32-bit <3=> Reserved
;// </e>
BCFG0_SETUP EQU 0
BCFG0_Val EQU 0x0000FBEF
;// <e> Bank Configuration 1 (BCFG1)
;// <o1.0..3> IDCY: Idle Cycles <0-15>
;// <o1.5..9> WST1: Wait States 1 <0-31>
;// <o1.11..15> WST2: Wait States 2 <0-31>
;// <o1.10> RBLE: Read Byte Lane Enable
;// <o1.26> WP: Write Protect
;// <o1.27> BM: Burst ROM
;// <o1.28..29> MW: Memory Width <0=> 8-bit <1=> 16-bit
;// <2=> 32-bit <3=> Reserved
;// </e>
BCFG1_SETUP EQU 0
BCFG1_Val EQU 0x0000FBEF
;// <e> Bank Configuration 2 (BCFG2)
;// <o1.0..3> IDCY: Idle Cycles <0-15>
;// <o1.5..9> WST1: Wait States 1 <0-31>
;// <o1.11..15> WST2: Wait States 2 <0-31>
;// <o1.10> RBLE: Read Byte Lane Enable
;// <o1.26> WP: Write Protect
;// <o1.27> BM: Burst ROM
;// <o1.28..29> MW: Memory Width <0=> 8-bit <1=> 16-bit
;// <2=> 32-bit <3=> Reserved
;// </e>
BCFG2_SETUP EQU 0
BCFG2_Val EQU 0x0000FBEF
;// <e> Bank Configuration 3 (BCFG3)
;// <o1.0..3> IDCY: Idle Cycles <0-15>
;// <o1.5..9> WST1: Wait States 1 <0-31>
;// <o1.11..15> WST2: Wait States 2 <0-31>
;// <o1.10> RBLE: Read Byte Lane Enable
;// <o1.26> WP: Write Protect
;// <o1.27> BM: Burst ROM
;// <o1.28..29> MW: Memory Width <0=> 8-bit <1=> 16-bit
;// <2=> 32-bit <3=> Reserved
;// </e>
BCFG3_SETUP EQU 0
BCFG3_Val EQU 0x0000FBEF
;// </e> End of EMC
; External Memory Pins definitions
PINSEL2 EQU 0xE002C014 ; PINSEL2 Address
PINSEL2_Val EQU 0x0E6149E4 ; CS0..3, OE, WE, BLS0..3,
; D0..31, A2..23, JTAG Pins
PRESERVE8
; Area Definition and Entry Point
; Startup Code must be linked first at Address at which it expects to
run.
AREA RESET, CODE, READONLY
ARM
; Exception Vectors
; Mapped to Address 0.
; Absolute addressing mode must be used.
; Dummy Handlers are implemented as infinite loops which can be modified.
Vectors LDR PC, Reset_Addr
LDR PC, Undef_Addr
LDR PC, SWI_Addr
LDR PC, PAbt_Addr
LDR PC, DAbt_Addr
NOP ; Reserved Vector
LDR PC, IRQ_Addr
LDR PC, [PC, #-0x0FF0] ; Vector from VicVectAddr
LDR PC, FIQ_Addr
IMPORT OS_CPU_ARM_ExceptUndefInstrHndlr
IMPORT OS_CPU_ARM_ExceptSwiHndlr
IMPORT OS_CPU_ARM_ExceptPrefetchAbortHndlr
IMPORT OS_CPU_ARM_ExceptDataAbortHndlr
IMPORT OS_CPU_ARM_ExceptIrqHndlr
IMPORT OS_CPU_ARM_ExceptFiqHndlr
Reset_Addr DCD Reset_Handler
Undef_Addr DCD OS_CPU_ARM_ExceptUndefInstrHndlr
SWI_Addr DCD OS_CPU_ARM_ExceptSwiHndlr
PAbt_Addr DCD OS_CPU_ARM_ExceptPrefetchAbortHndlr
DAbt_Addr DCD OS_CPU_ARM_ExceptDataAbortHndlr
nop
IRQ_Addr DCD OS_CPU_ARM_ExceptIrqHndlr
FIQ_Addr DCD OS_CPU_ARM_ExceptFiqHndlr
;Undef_Handler B Undef_Handler
;SWI_Handler B SWI_Handler
;PAbt_Handler B PAbt_Handler
;DAbt_Handler B DAbt_Handler
;IRQ_Handler B IRQ_Handler
;FIQ_Handler B FIQ_Handler
; Reset Handler
EXPORT Reset_Handler
Reset_Handler
; Setup External Memory Pins
IF
EF:EXTERNAL_MODE
LDR R0, =PINSEL2
LDR R1, =PINSEL2_Val
STR R1, [R0]
ENDIF
; Setup External Memory Controller
IF EMC_SETUP <> 0
LDR R0, =EMC_BASE
IF BCFG0_SETUP <> 0
LDR R1, =BCFG0_Val
STR R1, [R0, #BCFG0_OFS]
ENDIF
IF BCFG1_SETUP <> 0
LDR R1, =BCFG1_Val
STR R1, [R0, #BCFG1_OFS]
ENDIF
IF BCFG2_SETUP <> 0
LDR R1, =BCFG2_Val
STR R1, [R0, #BCFG2_OFS]
ENDIF
IF BCFG3_SETUP <> 0
LDR R1, =BCFG3_Val
STR R1, [R0, #BCFG3_OFS]
ENDIF
ENDIF ; EMC_SETUP
; Setup VPBDIV
IF VPBDIV_SETUP <> 0
LDR R0, =VPBDIV
LDR R1, =VPBDIV_Val
STR R1, [R0]
ENDIF
; Setup PLL
IF PLL_SETUP <> 0
LDR R0, =PLL_BASE
MOV R1, #0xAA
MOV R2, #0x55
; Configure and Enable PLL
MOV R3, #PLLCFG_Val
STR R3, [R0, #PLLCFG_OFS]
MOV R3, #PLLCON_PLLE
STR R3, [R0, #PLLCON_OFS]
STR R1, [R0, #PLLFEED_OFS]
STR R2, [R0, #PLLFEED_OFS]
; Wait until PLL Locked
PLL_Loop LDR R3, [R0, #PLLSTAT_OFS]
ANDS R3, R3, #PLLSTAT_PLOCK
BEQ PLL_Loop
; Switch to PLL Clock
MOV R3, #(PLLCON_PLLE:ORLLCON_PLLC)
STR R3, [R0, #PLLCON_OFS]
STR R1, [R0, #PLLFEED_OFS]
STR R2, [R0, #PLLFEED_OFS]
ENDIF ; PLL_SETUP
; Setup MAM
IF MAM_SETUP <> 0
LDR R0, =MAM_BASE
MOV R1, #MAMTIM_Val
STR R1, [R0, #MAMTIM_OFS]
MOV R1, #MAMCR_Val
STR R1, [R0, #MAMCR_OFS]
ENDIF ; MAM_SETUP
; Memory Mapping (when Interrupt Vectors are in RAM)
MEMMAP EQU 0xE01FC040 ; Memory Mapping Control
IFEF:REMAP
LDR R0, =MEMMAP
IFEF:EXTMEM_MODE
MOV R1, #3
ELIFEF:RAM_MODE
MOV R1, #2
ELSE
MOV R1, #1
ENDIF
STR R1, [R0]
ENDIF
; Initialise Interrupt System
; ...
; Setup Stack for each mode
LDR R0, =Stack_Top
; Enter Undefined Instruction Mode and set its Stack Pointer
MSR CPSR_c, #Mode_UND:OR:I_Bit:OR:F_Bit
MOV SP, R0
SUB R0, R0, #UND_Stack_Size
; Enter Abort Mode and set its Stack Pointer
MSR CPSR_c, #Mode_ABT:OR:I_Bit:OR:F_Bit
MOV SP, R0
SUB R0, R0, #ABT_Stack_Size
; Enter FIQ Mode and set its Stack Pointer
MSR CPSR_c, #Mode_FIQ:OR:I_Bit:OR:F_Bit
MOV SP, R0
SUB R0, R0, #FIQ_Stack_Size
; Enter IRQ Mode and set its Stack Pointer
MSR CPSR_c, #Mode_IRQ:OR:I_Bit:OR:F_Bit
MOV SP, R0
SUB R0, R0, #IRQ_Stack_Size
; Enter Supervisor Mode and set its Stack Pointer
MSR CPSR_c, #Mode_SVC:OR:I_Bit:OR:F_Bit
MOV SP, R0
SUB R0, R0, #SVC_Stack_Size
; Enter User Mode and set its Stack Pointer
MSR CPSR_c, #Mode_USR
IFEF:__MICROLIB
EXPORT __initial_sp
ELSE
MOV SP, R0
SUB SL, SP, #USR_Stack_Size
ENDIF
; Enter the C code
IMPORT __main
LDR R0, =__main
BX R0
IFEF:__MICROLIB
EXPORT __heap_base
EXPORT __heap_limit
ELSE
; User Initial Stack & Heap
AREA |.text|, CODE, READONLY
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + USR_Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ENDIF
END
Hi,
I am trying to port UCOS to LPC2103 using the latest code but I still can't get it to work.
I have rewritten my code to turn on LCD backlight with and
without the UCOS. The code without the UCOS just call the
BackLightingOn() and InitPort functions in the main() and this works
fine but I want to be able to get UCOS running. The code below shows a
task been created to turn on the backlight and delay, OSTimeDlyHMSM().
The code suppose contain several tasks but I have reduced to one so I
can figure out how to get UCOS running on the LPC2103 by turning on
the back light but I can't see the problem in the code.
The code for the main code is shown below.
#include "LPC2103.h"
#include "os_cpu.h"
#include "cpu.h"
#include "app_cfg.h"
#include "ucos_ii.h"
#define Fosc 16000000 //Crystal
frequence,10MHz~25MHz£¬should be the same as actual status.
#define Fcclk (Fosc * 3) //System
frequence,should be (1~32)multiples of Fosc,and should be equal or
less than 60MHz.
#define Fpclk (Fcclk / 4) * 1 //VPB clock
frequence , must be 1¡¢2¡¢4 multiples of (Fcclk / 4).
static OS_STK AppTaskStartStk[APP_TASK_START_STK_SIZE];
static void AppTaskStart (void *p_arg);
void tc3 (void){
T3IR = 1; // Clear interrupt flag
OSTimeTick();
FIOPIN1^=0x08; //debugging
VICVectAddr = 0; // Acknowledge Interrupt
}
void StartTicker(void){
T3MR0 = Fpclk/OS_TICKS_PER_SEC-1; // 1mSec = 15000-1 counts at 15
Mhz PCLK
T3MCR = 3; // Interrupt and Reset on MR0
T3TCR = 1; // Timer0 Enable
VICVectAddr0 = (unsigned long)tc3; // set interrupt vector in 0
VICVectCntl0 = 0x20 | VIC_TIMER3; // use it for Timer 0
Interrupt
VICIntEnable = 1<<VIC_TIMER3; // Enable Timer0 Interrupt
}
void BackLightingOn(void){
// BackLightingOnFlag=1;
// BackLightingOnTimer=0;
IOSET=0x04000000;
FIOSET3=0x04;
}
void Initport(void){
IODIR=0x0C81000C;
FIODIR0=0x0C;
FIODIR2=0x81;
FIODIR3=0x0C;
FIOPIN2=0x00;
FIOPIN3=0x00;
FIODIR1=0x08;
FIOPIN1=0x00;
}
void BSP_IntDisAll (void)
{
VICIntEnClr = 0xFFFFFFFFL; /*
Disable ALL interrupts */
}
int main (void){
BSP_IntDisAll(); //disable interrupts
OSInit();
OSTaskCreateExt(AppTaskStart, /* Create
the start task */
(void *)0,
(OS_STK *)&AppTaskStartStk[APP_TASK_START_STK_SIZE
- 1],
APP_TASK_START_PRIO,
APP_TASK_START_PRIO,
(OS_STK *)&AppTaskStartStk[0],
APP_TASK_START_STK_SIZE,
(void *)0,
OS_TASK_OPT_STK_CHK | OS_TASK_OPT_STK_CLR);
OSStart();
return (0);
}
static void AppTaskStart (void *p_arg)
{
(void)p_arg;
OS_CPU_InitExceptVect();
SCS=0x03;
if( WDMOD & 0x04 ){
WDMOD &= ~0x04;
}
StartTicker();
//BSP_Init(); /*
Initialize BSP functions */
Initport(); // Initialise the ports
/* Create application tasks
*/
while (1) { /* Task body,
always written as an infinite loop. */
BackLightingOn(); // Turn Backlight On
OSTimeDlyHMSM(0, 0, 0, 5);
}
}
/*
********************************************************************************\
*************************
* OS_CPU_ExceptHndlr()
*
* Description : Handle any exceptions.
*
* Argument(s) : except_id ARM exception type:
*
* OS_CPU_ARM_EXCEPT_RESET
0x00
* OS_CPU_ARM_EXCEPT_UNDEF_INSTR
0x01
* OS_CPU_ARM_EXCEPT_SWI
0x02
* OS_CPU_ARM_EXCEPT_PREFETCH_ABORT
0x03
* OS_CPU_ARM_EXCEPT_DATA_ABORT
0x04
* OS_CPU_ARM_EXCEPT_ADDR_ABORT
0x05
* OS_CPU_ARM_EXCEPT_IRQ
0x06
* OS_CPU_ARM_EXCEPT_FIQ
0x07
*
* Return(s) : none.
*
* Caller(s) : OS_CPU_ARM_EXCEPT_HANDLER(), which is declared in
os_cpu_a.s.
********************************************************************************\
*************************
*/
void OS_CPU_ExceptHndlr (CPU_INT32U except_id)
{
CPU_FNCT_VOID pfnct;
if (except_id == OS_CPU_ARM_EXCEPT_IRQ) {
pfnct = (CPU_FNCT_VOID)VICVectAddr; /*
Read the interrupt vector from the VIC */
while (pfnct != (CPU_FNCT_VOID)0) { /*
Make sure we don't have a NULL pointer */
(*pfnct)(); /*
Execute the ISR for the interrupting device */
VICVectAddr = 1; /*
Acknowlege the VIC interrupt */
pfnct = (CPU_FNCT_VOID)VICVectAddr; /*
Read the interrupt vector from the VIC */
}
} else {
/*
Infinite loop on other exceptions. */
/*
Should be replaced by other behavior (reboot, etc.) */
while (1) {
;
}
}
}
Added after 46 seconds:
My startup script is shown below.
;/*****************************************************************************/
;/* STARTUP.S: Startup file for Philips LPC2000
*/
;/*****************************************************************************/
;/* <<< Use Configuration Wizard in Context Menu >>>
*/
;/*****************************************************************************/
;/* This file is part of the uVision/ARM development tools.
*/
;/* Copyright (c) 2005-2007 Keil Software. All rights reserved.
*/
;/* This software may only be used under the terms of a valid,
current, */
;/* end user licence from KEIL for a compatible version of KEIL
software */
;/* development tools. Nothing else gives you the right to use this
software. */
;/*****************************************************************************/
;/*
; * The STARTUP.S code is executed after CPU Reset. This file may be
; * translated with the following SET symbols. In uVision these SET
; * symbols are entered under Options - ASM - Define.
; *
; * REMAP: when set the startup code initializes the register MEMMAP
; * which overwrites the settings of the CPU configuration pins. The
; * startup and interrupt vectors are remapped from:
; * 0x00000000 default setting (not remapped)
; * 0x80000000 when EXTMEM_MODE is used
; * 0x40000000 when RAM_MODE is used
; *
; * EXTMEM_MODE: when set the device is configured for code execution
; * from external memory starting at address 0x80000000.
; *
; * RAM_MODE: when set the device is configured for code execution
; * from on-chip RAM starting at address 0x40000000.
; *
; * EXTERNAL_MODE: when set the PIN2SEL values are written that enable
; * the external BUS at startup.
; */
; Standard definitions of Mode bits and Interrupt (I & F) flags in PSRs
Mode_USR EQU 0x10
Mode_FIQ EQU 0x11
Mode_IRQ EQU 0x12
Mode_SVC EQU 0x13
Mode_ABT EQU 0x17
Mode_UND EQU 0x1B
Mode_SYS EQU 0x1F
I_Bit EQU 0x80 ; when I bit is set, IRQ is
disabled
F_Bit EQU 0x40 ; when F bit is set, FIQ is
disabled
;// <h> Stack Configuration (Stack Sizes in Bytes)
;// <o0> Undefined Mode <0x0-0xFFFFFFFF:8>
;// <o1> Supervisor Mode <0x0-0xFFFFFFFF:8>
;// <o2> Abort Mode <0x0-0xFFFFFFFF:8>
;// <o3> Fast Interrupt Mode <0x0-0xFFFFFFFF:8>
;// <o4> Interrupt Mode <0x0-0xFFFFFFFF:8>
;// <o5> User/System Mode <0x0-0xFFFFFFFF:8>
;// </h>
UND_Stack_Size EQU 0x00000000
SVC_Stack_Size EQU 0x00000008
ABT_Stack_Size EQU 0x00000000
FIQ_Stack_Size EQU 0x00000000
IRQ_Stack_Size EQU 0x00000080
USR_Stack_Size EQU 0x00000400
ISR_Stack_Size EQU (UND_Stack_Size + SVC_Stack_Size +
ABT_Stack_Size + \
FIQ_Stack_Size + IRQ_Stack_Size)
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE USR_Stack_Size
__initial_sp SPACE ISR_Stack_Size
Stack_Top
;// <h> Heap Configuration
;// <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF>
;// </h>
Heap_Size EQU 0x00000000
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
; VPBDIV definitions
VPBDIV EQU 0xE01FC100 ; VPBDIV Address
;// <e> VPBDIV Setup
;// Peripheral Bus Clock Rate
;// <o1.0..1> VPBDIV: VPB Clock
;// <0=> VPB Clock = CPU Clock / 4
;// <1=> VPB Clock = CPU Clock
;// <2=> VPB Clock = CPU Clock / 2
;// <o1.4..5> XCLKDIV: XCLK Pin
;// <0=> XCLK Pin = CPU Clock / 4
;// <1=> XCLK Pin = CPU Clock
;// <2=> XCLK Pin = CPU Clock / 2
;// </e>
VPBDIV_SETUP EQU 0
VPBDIV_Val EQU 0x00000000
; Phase Locked Loop (PLL) definitions
PLL_BASE EQU 0xE01FC080 ; PLL Base Address
PLLCON_OFS EQU 0x00 ; PLL Control Offset
PLLCFG_OFS EQU 0x04 ; PLL Configuration Offset
PLLSTAT_OFS EQU 0x08 ; PLL Status Offset
PLLFEED_OFS EQU 0x0C ; PLL Feed Offset
PLLCON_PLLE EQU (1<<0) ; PLL Enable
PLLCON_PLLC EQU (1<<1) ; PLL Connect
PLLCFG_MSEL EQU (0x1F<<0) ; PLL Multiplier
PLLCFG_PSEL EQU (0x03<<5) ; PLL Divider
PLLSTAT_PLOCK EQU (1<<10) ; PLL Lock Status
;// <e> PLL Setup
;// <o1.0..4> MSEL: PLL Multiplier Selection
;// <1-32><#-1>
;// M Value
;// <o1.5..6> PSEL: PLL Divider Selection
;// <0=> 1 <1=> 2 <2=> 4 <3=> 8
;// P Value
;// </e>
PLL_SETUP EQU 1
PLLCFG_Val EQU 0x00000024
; Memory Accelerator Module (MAM) definitions
MAM_BASE EQU 0xE01FC000 ; MAM Base Address
MAMCR_OFS EQU 0x00 ; MAM Control Offset
MAMTIM_OFS EQU 0x04 ; MAM Timing Offset
;// <e> MAM Setup
;// <o1.0..1> MAM Control
;// <0=> Disabled
;// <1=> Partially Enabled
;// <2=> Fully Enabled
;// Mode
;// <o2.0..2> MAM Timing
;// <0=> Reserved <1=> 1 <2=> 2 <3=> 3
;// <4=> 4 <5=> 5 <6=> 6 <7=> 7
;// Fetch Cycles
;// </e>
MAM_SETUP EQU 1
MAMCR_Val EQU 0x00000002
MAMTIM_Val EQU 0x00000004
; External Memory Controller (EMC) definitions
EMC_BASE EQU 0xFFE00000 ; EMC Base Address
BCFG0_OFS EQU 0x00 ; BCFG0 Offset
BCFG1_OFS EQU 0x04 ; BCFG1 Offset
BCFG2_OFS EQU 0x08 ; BCFG2 Offset
BCFG3_OFS EQU 0x0C ; BCFG3 Offset
;// <e> External Memory Controller (EMC)
EMC_SETUP EQU 0
;// <e> Bank Configuration 0 (BCFG0)
;// <o1.0..3> IDCY: Idle Cycles <0-15>
;// <o1.5..9> WST1: Wait States 1 <0-31>
;// <o1.11..15> WST2: Wait States 2 <0-31>
;// <o1.10> RBLE: Read Byte Lane Enable
;// <o1.26> WP: Write Protect
;// <o1.27> BM: Burst ROM
;// <o1.28..29> MW: Memory Width <0=> 8-bit <1=> 16-bit
;// <2=> 32-bit <3=> Reserved
;// </e>
BCFG0_SETUP EQU 0
BCFG0_Val EQU 0x0000FBEF
;// <e> Bank Configuration 1 (BCFG1)
;// <o1.0..3> IDCY: Idle Cycles <0-15>
;// <o1.5..9> WST1: Wait States 1 <0-31>
;// <o1.11..15> WST2: Wait States 2 <0-31>
;// <o1.10> RBLE: Read Byte Lane Enable
;// <o1.26> WP: Write Protect
;// <o1.27> BM: Burst ROM
;// <o1.28..29> MW: Memory Width <0=> 8-bit <1=> 16-bit
;// <2=> 32-bit <3=> Reserved
;// </e>
BCFG1_SETUP EQU 0
BCFG1_Val EQU 0x0000FBEF
;// <e> Bank Configuration 2 (BCFG2)
;// <o1.0..3> IDCY: Idle Cycles <0-15>
;// <o1.5..9> WST1: Wait States 1 <0-31>
;// <o1.11..15> WST2: Wait States 2 <0-31>
;// <o1.10> RBLE: Read Byte Lane Enable
;// <o1.26> WP: Write Protect
;// <o1.27> BM: Burst ROM
;// <o1.28..29> MW: Memory Width <0=> 8-bit <1=> 16-bit
;// <2=> 32-bit <3=> Reserved
;// </e>
BCFG2_SETUP EQU 0
BCFG2_Val EQU 0x0000FBEF
;// <e> Bank Configuration 3 (BCFG3)
;// <o1.0..3> IDCY: Idle Cycles <0-15>
;// <o1.5..9> WST1: Wait States 1 <0-31>
;// <o1.11..15> WST2: Wait States 2 <0-31>
;// <o1.10> RBLE: Read Byte Lane Enable
;// <o1.26> WP: Write Protect
;// <o1.27> BM: Burst ROM
;// <o1.28..29> MW: Memory Width <0=> 8-bit <1=> 16-bit
;// <2=> 32-bit <3=> Reserved
;// </e>
BCFG3_SETUP EQU 0
BCFG3_Val EQU 0x0000FBEF
;// </e> End of EMC
; External Memory Pins definitions
PINSEL2 EQU 0xE002C014 ; PINSEL2 Address
PINSEL2_Val EQU 0x0E6149E4 ; CS0..3, OE, WE, BLS0..3,
; D0..31, A2..23, JTAG Pins
PRESERVE8
; Area Definition and Entry Point
; Startup Code must be linked first at Address at which it expects to
run.
AREA RESET, CODE, READONLY
ARM
; Exception Vectors
; Mapped to Address 0.
; Absolute addressing mode must be used.
; Dummy Handlers are implemented as infinite loops which can be modified.
Vectors LDR PC, Reset_Addr
LDR PC, Undef_Addr
LDR PC, SWI_Addr
LDR PC, PAbt_Addr
LDR PC, DAbt_Addr
NOP ; Reserved Vector
LDR PC, IRQ_Addr
LDR PC, [PC, #-0x0FF0] ; Vector from VicVectAddr
LDR PC, FIQ_Addr
IMPORT OS_CPU_ARM_ExceptUndefInstrHndlr
IMPORT OS_CPU_ARM_ExceptSwiHndlr
IMPORT OS_CPU_ARM_ExceptPrefetchAbortHndlr
IMPORT OS_CPU_ARM_ExceptDataAbortHndlr
IMPORT OS_CPU_ARM_ExceptIrqHndlr
IMPORT OS_CPU_ARM_ExceptFiqHndlr
Reset_Addr DCD Reset_Handler
Undef_Addr DCD OS_CPU_ARM_ExceptUndefInstrHndlr
SWI_Addr DCD OS_CPU_ARM_ExceptSwiHndlr
PAbt_Addr DCD OS_CPU_ARM_ExceptPrefetchAbortHndlr
DAbt_Addr DCD OS_CPU_ARM_ExceptDataAbortHndlr
nop
IRQ_Addr DCD OS_CPU_ARM_ExceptIrqHndlr
FIQ_Addr DCD OS_CPU_ARM_ExceptFiqHndlr
;Undef_Handler B Undef_Handler
;SWI_Handler B SWI_Handler
;PAbt_Handler B PAbt_Handler
;DAbt_Handler B DAbt_Handler
;IRQ_Handler B IRQ_Handler
;FIQ_Handler B FIQ_Handler
; Reset Handler
EXPORT Reset_Handler
Reset_Handler
; Setup External Memory Pins
IF
EF:EXTERNAL_MODELDR R0, =PINSEL2
LDR R1, =PINSEL2_Val
STR R1, [R0]
ENDIF
; Setup External Memory Controller
IF EMC_SETUP <> 0
LDR R0, =EMC_BASE
IF BCFG0_SETUP <> 0
LDR R1, =BCFG0_Val
STR R1, [R0, #BCFG0_OFS]
ENDIF
IF BCFG1_SETUP <> 0
LDR R1, =BCFG1_Val
STR R1, [R0, #BCFG1_OFS]
ENDIF
IF BCFG2_SETUP <> 0
LDR R1, =BCFG2_Val
STR R1, [R0, #BCFG2_OFS]
ENDIF
IF BCFG3_SETUP <> 0
LDR R1, =BCFG3_Val
STR R1, [R0, #BCFG3_OFS]
ENDIF
ENDIF ; EMC_SETUP
; Setup VPBDIV
IF VPBDIV_SETUP <> 0
LDR R0, =VPBDIV
LDR R1, =VPBDIV_Val
STR R1, [R0]
ENDIF
; Setup PLL
IF PLL_SETUP <> 0
LDR R0, =PLL_BASE
MOV R1, #0xAA
MOV R2, #0x55
; Configure and Enable PLL
MOV R3, #PLLCFG_Val
STR R3, [R0, #PLLCFG_OFS]
MOV R3, #PLLCON_PLLE
STR R3, [R0, #PLLCON_OFS]
STR R1, [R0, #PLLFEED_OFS]
STR R2, [R0, #PLLFEED_OFS]
; Wait until PLL Locked
PLL_Loop LDR R3, [R0, #PLLSTAT_OFS]
ANDS R3, R3, #PLLSTAT_PLOCK
BEQ PLL_Loop
; Switch to PLL Clock
MOV R3, #(PLLCON_PLLE:OR
LLCON_PLLC)STR R3, [R0, #PLLCON_OFS]
STR R1, [R0, #PLLFEED_OFS]
STR R2, [R0, #PLLFEED_OFS]
ENDIF ; PLL_SETUP
; Setup MAM
IF MAM_SETUP <> 0
LDR R0, =MAM_BASE
MOV R1, #MAMTIM_Val
STR R1, [R0, #MAMTIM_OFS]
MOV R1, #MAMCR_Val
STR R1, [R0, #MAMCR_OFS]
ENDIF ; MAM_SETUP
; Memory Mapping (when Interrupt Vectors are in RAM)
MEMMAP EQU 0xE01FC040 ; Memory Mapping Control
IF
EF:REMAPLDR R0, =MEMMAP
IF
EF:EXTMEM_MODEMOV R1, #3
ELIF
EF:RAM_MODEMOV R1, #2
ELSE
MOV R1, #1
ENDIF
STR R1, [R0]
ENDIF
; Initialise Interrupt System
; ...
; Setup Stack for each mode
LDR R0, =Stack_Top
; Enter Undefined Instruction Mode and set its Stack Pointer
MSR CPSR_c, #Mode_UND:OR:I_Bit:OR:F_Bit
MOV SP, R0
SUB R0, R0, #UND_Stack_Size
; Enter Abort Mode and set its Stack Pointer
MSR CPSR_c, #Mode_ABT:OR:I_Bit:OR:F_Bit
MOV SP, R0
SUB R0, R0, #ABT_Stack_Size
; Enter FIQ Mode and set its Stack Pointer
MSR CPSR_c, #Mode_FIQ:OR:I_Bit:OR:F_Bit
MOV SP, R0
SUB R0, R0, #FIQ_Stack_Size
; Enter IRQ Mode and set its Stack Pointer
MSR CPSR_c, #Mode_IRQ:OR:I_Bit:OR:F_Bit
MOV SP, R0
SUB R0, R0, #IRQ_Stack_Size
; Enter Supervisor Mode and set its Stack Pointer
MSR CPSR_c, #Mode_SVC:OR:I_Bit:OR:F_Bit
MOV SP, R0
SUB R0, R0, #SVC_Stack_Size
; Enter User Mode and set its Stack Pointer
MSR CPSR_c, #Mode_USR
IF
EF:__MICROLIBEXPORT __initial_sp
ELSE
MOV SP, R0
SUB SL, SP, #USR_Stack_Size
ENDIF
; Enter the C code
IMPORT __main
LDR R0, =__main
BX R0
IF
EF:__MICROLIBEXPORT __heap_base
EXPORT __heap_limit
ELSE
; User Initial Stack & Heap
AREA |.text|, CODE, READONLY
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + USR_Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ENDIF
END