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[SOLVED] Junk data in MIG (Virtex7)

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rahdirs

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Hi,

I'm working with MIG v2.1.While trying to write to DDR3,there is some wierd data which is coming at ddr3_dq signal which is getting written to DDR3.

This is happening even before calibration signal becomes high & also after it goes high.

Junk data before calibration signal goes high
junk_before_calib.PNG

Junk data after calibration signal goes high
junk_part2.PNG

Obviously,i'm reading that junking data when i give read command
Junk_read.PNG
 
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vGoodtimes

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Are you talking about the periodic calibration read?

IIRC, Xilinx documents what you see in pic 2. It is a periodic read used to maintain read calibration.
 

rahdirs

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It is a periodic read used to maintain read calibration.

If ip_core is writing that data for read calibration,should i be reading back that data at UI side (in app_rd_data)?

In the attached snapshot see,the time app_rd_data_valid is high(when i've written only 8 data words = 51.2 ns).
 

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  • read_calibration.PNG
    read_calibration.PNG
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Did you write anything to the DDR RAM before reading?

I'm also not sure where vGoodtimes came up with this being periodic read calibration data. The periodic read just reads whatever last address was used according to UG586 v2.1 page 149. If you don't write anything to the memory before the 1 us period then there will be a read transaction if the dynamic calibration was enabled. This read though does not change data that was previously written its used to adjust the DQS timing. If the core were to write calibration data to the memory that would be a huge problem for most users.
 

rahdirs

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Did you write anything to the DDR RAM before reading?

Yes,after calibration is done,i'm writing 8 data words at 8 different address locations.This data while,i give at UI side, i could trace it till ddr3_dq signal (fpga-ddr3 interface).

But while reading,i'm giving the written address locations & am getting some wierd data.
And while writing data at UI side, i could see my data at ddr3_dq signal, i also see a lot of wierd data at that signal which i'm not giving at UI side.

Read data waveform is attached above(post 3)
 

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  • timing diagram.PNG
    timing diagram.PNG
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  • write_data_phy.PNG
    write_data_phy.PNG
    71.5 KB · Views: 5

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Did you simulate the example design produced by MIG, before modifying it to write/read the data you want?
 

rahdirs

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Hi,

Yes.I modified his top module by removing out his traffic generator & connecting my data signal to the ip_core.

His simulation i only checked rd/wr at 1 address location & just saw that he has a signal tg_compare_error which never went high.So,his simulation was correct.
 

vGoodtimes

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It looks like the write mask is set to 'U'. I'm guessing that the DQ lines toggle, but the DM lines are not correct. There isn't enough info as you don't have any waveforms of the writes.
 
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rahdirs

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It looks like the write mask is set to 'U'.

If you don't want to mask any data,i was thinking you can leave it as 'U'.

But the dm lines are not correct.

What do you mean ?

There isn't enough info as you don't have any waveforms of the writes.
Attached snapshots of writes

Snapshot 1: my write data at UI side : app_wr_data
Snapshot 2: my write data going to ddr3_dq signal (fpga-ddr3 interface) after some time.
Snapshot 3: just before my data is passed onto ddr3_dq signal,there is some wierd data.
Snapshot4: my write data going into micron memory model dq signal
Snapshot 5: that junk data just before my data going into memory model.
 

Attachments

  • app_write.PNG
    app_write.PNG
    64.5 KB · Views: 5
  • dq_ddr3_my_data.PNG
    dq_ddr3_my_data.PNG
    52.2 KB · Views: 4
  • dq_ddr3_junk.PNG
    dq_ddr3_junk.PNG
    53.3 KB · Views: 4
  • ddr_dq_junk_data.PNG
    ddr_dq_junk_data.PNG
    69.6 KB · Views: 3
  • ddr_dq_my_data.PNG
    ddr_dq_my_data.PNG
    68.9 KB · Views: 4

rahdirs

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It looks like the write mask is set to 'U'. I'm guessing that the DQ lines toggle, but the DM lines are not correct. There isn't enough info as you don't have any waveforms of the writes.

Yeah,that was the problem.
Now,i've set my app_wdf_mask bus to "000...0" & also set data mask(dm bits) to 0.

In ug586 manual,he was saying,if you are not driving dm bits in fpga,pull them down with a pull down resistor on your board.

So,i was keeping it undriven.But,now i am assigning it 0 & i'm able to read my data correctly.

But,the 1st data word that i read is still some wierd data & from the 2nd data word onwards,i'm reading my data.

P.S: that wierd data i'm talking about is the same wierd dataword in snapshot 3 of post #9.

Snapshot1: wierd data read in 1st dataword.
Snapshot2: my data from 2nd dataword onwards.

Is the data i'm reading in the 1st data word "444444222222.............999999" is because of some calibration or something ?


That data "444444222222.............999999" is going before my data into ddr3 from ddr3_dq signal as shown in snapshot3 in #9


---------------------------- Edited --------------------------------
Looking back at his example design simulation,he was keeping wdf_mask as "000...0" but his dm bits were "XXX",so i think my problem was because of my wdf_mask remaining as U
 

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  • rd_junk_data.PNG
    rd_junk_data.PNG
    63.8 KB · Views: 4
  • rd_my_data.PNG
    rd_my_data.PNG
    62.8 KB · Views: 4
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vGoodtimes

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From the read/write sim waveforms, you write to locations 8, 16, 24 ... and then read from 0, 8, 16 ...
 

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