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juction current exceeds 'imax'

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arong00

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imax imelt

When I design a simple delayed RZ logic circuit(just simple inverters and Nand gates), I meet following warning. How to solve these problems? (IBM 130nm process)

juction current exceeds 'imelt'
juction current exceeds 'imax'

I checked model files and all imax and imelt definded as following:
bondpad.scs imax = 1e15
divpnp.scs imax = 1e6*iboverie*tota
esdvpnp.scs imax = 1e15
havar.scs imax = 1e15
nwres.scs imax = 1e15
opndres.scs imax = 1e15
sblkndres.scs imax = 1e15
divpnp.scs imelt = 10

Do I need to increase the value of imax and imelt? since the circuit is really simple but because for above problem, I am not be able to get the simulation results.

Thanks!
 

rajanarender_suram

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Somewhere the substrate junction is forward biased..... i think so
 

dick_freebird

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These are warning, not error flags; the simulation should complete. However you
should never hit the imax values (not even the divpnp at 10 amps) in a well
behaved circuit. The problem is more likely a model flaw, singularity or blowup at
a point outside the characterized / fitted space, that is stepped into by the numerical
solution overshoot.

You might begin with tightening timestep and accuracy settings, make sure all
nodes have a reasonable capacitance and all branches a reasonable resistance,
and so on.
 

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