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JTAG programming of EPCS config memories

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davorin

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Someone has acopy of an application note from Altera describing how to program EPCS series config memories through JTAG via Cyclone FPGAs?
 

Ehhmm..I meant what I said (o;

Only connection is JTAG to Cyclone...and FPGA programs EPCS...
 

> how to program EPCS series config memories through JTAG via Cyclone FPGAs?

The method does not exist.
See Figre 5-25 cyc_c51013.pdf.
 

It does exist!!!
Don't tell something you don't know for sure (o;


Just ask your local Altera FAE for the Serialflash loader .sof files...
 

The config bus of EPCS has been independent of the JTAG chain of Cyclon.
And, control of the config bus for EPCS cannot be performed from a JTAG chain.

Or,EPCS configure using via JTAG boundary-scan ?

Usually, EPCS is configure using ByteBlaster2.
 

The EPCS devices can be accessed through JTAG accessing Cyclone internal registers...there's also the EPCS driver in the new NIOSII kit allowing the CPU core read/write to the EPCS memory as well...


Here's something I found:

hxxp://www.fpga.ch/samples_jtag.php
 

If you have SPOC Builder, please build with the composition of NIOS+ASMI.
The answer for which you ask is in generated file !(evaluation version can it.)

This question of yours became a stimulus good for me.
I am thankful to you !
 

we have a way to program this using a nios design. We jtag load a design into the chip with a serial port and a processor, we then use the pc to send the file (we generate an .rpd file using quartus.) to the chip. If you used the jtag debug port instead of serial port then this would work. You may need to write a JTAG driver for your own software to program over that port.
 

Application Notes
AN 379: Active Serial Memory Interface Controller Reference Design (ver 1.0, Mar 2005, 190 KB)

h**p://www.altera.com/literature/lit-cyc.jsp
 

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