Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
I could see a design,where johson counter is used as the clock divider? Does it offer any advantages...I could only find that johnson counter also has 1 bit change between the count sequences...
I think johnson counter are used for clock dividing, because they are faster, because we do not need much logic for this. At least compared to a binary counter.
e.g. for dividing by four you just need 2 FF and an inverter. If the FF would have an inverting output you do only need the two FF and loop the output of one FF to the input of the other FF.