anjali
Full Member level 3
hi all,
i'm searching for a job in the field of VLSI design.
i'm doing good projects in the ASIC design flow. (specs to P&R stage)
contact me if interested.
SKILL SET:
•RTL coding, linting, Verification, code coverage & Automation.
•ASIC synthesis, Scan chain insertion, ATPG vector generation using Design Compiler and netlist simulations.
•Static timing analysis using DC & PT.
•Chip floor planning, placement, CTS and routing using SOC Encounter.
•Formal verification of the generated netlist in each stage with golden RTL, using conformal.
•Checking for LVS and DRCs for the GDSII using Hercules and LayoutPlus.
•FPGA synthesis, placement & Routing using ISE.
•Good knowledge in System Design.
•Device modeling with xtensa RISC processors using the tool XTMP.
Languages
Hardware Description Languages : Verilog, System C
Scripting Languages : PERL, TCL/TK, C-Shell
Assembly Programming : Xtensa RISC processor, 8085, 8051, ADSP 2181
Programming Languages : C, C++
Operating Systems : UNIX, Linux, Windows NT
EDA Tools
HDL simulators : Verilog-XL, NC-Verilog
Linting & coverage tools : HAL, Surelint, Surecov, ICTC
Synthesis Tools : Synopsys DC, Tetramax , PT, Synplify_pro(FPGA)
Backend Tools : SOC Encounter, LayoutPlus, Herculus, ISE(FPGA)
i'm searching for a job in the field of VLSI design.
i'm doing good projects in the ASIC design flow. (specs to P&R stage)
contact me if interested.
SKILL SET:
•RTL coding, linting, Verification, code coverage & Automation.
•ASIC synthesis, Scan chain insertion, ATPG vector generation using Design Compiler and netlist simulations.
•Static timing analysis using DC & PT.
•Chip floor planning, placement, CTS and routing using SOC Encounter.
•Formal verification of the generated netlist in each stage with golden RTL, using conformal.
•Checking for LVS and DRCs for the GDSII using Hercules and LayoutPlus.
•FPGA synthesis, placement & Routing using ISE.
•Good knowledge in System Design.
•Device modeling with xtensa RISC processors using the tool XTMP.
Languages
Hardware Description Languages : Verilog, System C
Scripting Languages : PERL, TCL/TK, C-Shell
Assembly Programming : Xtensa RISC processor, 8085, 8051, ADSP 2181
Programming Languages : C, C++
Operating Systems : UNIX, Linux, Windows NT
EDA Tools
HDL simulators : Verilog-XL, NC-Verilog
Linting & coverage tools : HAL, Surelint, Surecov, ICTC
Synthesis Tools : Synopsys DC, Tetramax , PT, Synplify_pro(FPGA)
Backend Tools : SOC Encounter, LayoutPlus, Herculus, ISE(FPGA)
