jk flip flop problem

[saharnaz]

Hello
I am trying to make a jk flip flop with cadence and designed it with cadence, exactly like what I saw in the internet. but it's not working!I have attached a picture of my circuit. inside the blocks, are the 3 input nand and 2 input nand circuits which are fine and working perfectly when tested outside this circuit. I have set j and k both as vdd (logical 1) so it should toggle whith each clock rise. but it doesn't. can you tell me what I'm doing wrong?
Thank you very much
Saharnaz

 

[barry]

What are your initial conditions?

Assume Q=0, Qbar=1, clock=0

So, J0.out=1, J1.out=1

After the rising edge of clock, J0.out=0, Q=1, J1.out=0, Qbar=1(still!)

This doesn't look right. I think your logic is wrong.

What do your signals look like?