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JK flip flop as a frequency divided-by-2 block

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Spikiera

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Hello everyone,

I am having some serious issue trying to use a single JK flip flop to build a frequency divider (divide by 2). Somehow my output "Q" either does not toggle at all or toggles at the wrong frequency. Or, the output just doesn't make sense.

The JK flip flop I use looks like the following:
IMG_1283.JPG

It is a 4 NAND gates JK FF. I tie both J and K node to VDD, and the CLK is my input. According to many textbook or on-line resources, the output should toggle at half of the CLK frequency.

I run the design in Cadence analog design environment but the output just doesn't toggle correctly. The NAND gates are CMOS NAND gate...3 parallel PMOS pull up and 3 series NMOS pull down for example. All 4 NAND gates use the same sizing.

It is driving me crazy, I've worked on this the whole day. I am now doubting this topology even works. It looks like it is difficult to maintain good oscillation and the feedback usually can destroy the way the signal toggles. It doesn't look like an edge trigger FF either. I think DFF would work much better, but has anyone done this before and worked?

I cannot figure out the timing requirements for each gate, is the timing for the 4 NAND gate very very important?

Please help....:bang::bang::bang:

Thank you guys so much!
 

That should work.
Depending on the gate delays, there will be an upper frequency limit where things may start to go "funny".

A D flip flop will also divide by two if you connect the D input to the not Q output.
 

Hi,

or toggles at the wrong frequency

What input frequency did you use?
And what toggle frequency did you see?

Klaus
 

That looks like a half-latch to me, not a flip-flop. You might
be seeing self-toggling from the feedback as your half-latch
is level triggered, not edge triggered, on CLK.

**broken link removed**
 
That looks like a half-latch to me, not a flip-flop. You might
be seeing self-toggling from the feedback as your half-latch
is level triggered, not edge triggered, on CLK.

**broken link removed**

Hi dick_freebird, you are absolutely right. Thank you so so much for your input! You saved my day.

The results I was seeing had a lot of self-toggling and it seemed that the circuit was not sure what states it should be in.

After I add another stage, it worked.

A lot of on-line resources and textbook should really change the wording and presentation because with only one stage of JK, it cannot really be used as frequency divider...

Or maybe I am wrong again lol :bang::bang:
 

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