Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

jitter effect in continuous time sigma delta modulator

Status
Not open for further replies.

sixth

Member level 4
Joined
Feb 16, 2006
Messages
70
Helped
10
Reputation
20
Reaction score
0
Trophy points
1,286
Activity points
2,118
I have designed three continuuos time sigma delta modulators with the same structure, the same coefficients, same input signal and the same sampling frequency, the only difference is that the quantizers they use is 1 bit , 3bits and 5bits respectively. All the quantizers are described bye verilog-a and they have the same delay(0.1ns,the sample frequency is 48MHz), the same rising and falling time. I had think that the modulators with 3bits and 5bits quantizers would have better SNR performance than the single bit one. But simulation shows that they have the same SNR performance( the FFT points is also identical). I am really puzzled by this problem. Can anybody tell me the reason? thank you very much!
 

tsb_nph

Full Member level 2
Joined
Mar 9, 2005
Messages
125
Helped
23
Reputation
46
Reaction score
5
Trophy points
1,298
Location
USA
Activity points
2,820
sixth said:
I have designed three continuuos time sigma delta modulators with the same structure, the same coefficients, same input signal and the same sampling frequency, the only difference is that the quantizers they use is 1 bit , 3bits and 5bits respectively. All the quantizers are described bye verilog-a and they have the same delay(0.1ns,the sample frequency is 48MHz), the same rising and falling time. I had think that the modulators with 3bits and 5bits quantizers would have better SNR performance than the single bit one. But simulation shows that they have the same SNR performance( the FFT points is also identical). I am really puzzled by this problem. Can anybody tell me the reason? thank you very much!

Hi sixth,
There is something wrong with your simulations as the results are surely incorrect. For a mult-bit comparator implementation, the SNR increases by 6 dB for a 1 bit increase in the comparator resolution, which means that the 3 bit will have 12 dB increase in SNR while the 5 bit will have 24 dB increase in SNR as compared to the 1 bit implemnetation.
To debug the problem more, can you explain your simulation setup (Cadence/Matlab etc) in more detail?
A couple of questions to help in understanding your setup better :
i) Are you using ideal integrators/low pass filters in the loop filter?
ii) Are you implemneting multi-bit DAC correctly? Are you taking the FFT correctly for output of each of the three cases ( 1 bit, 3 bit and 5 bit outputs)?

Bharath
 

sixth

Member level 4
Joined
Feb 16, 2006
Messages
70
Helped
10
Reputation
20
Reaction score
0
Trophy points
1,286
Activity points
2,118
tsb_nph said:
Hi sixth,
There is something wrong with your simulations as the results are surely incorrect. For a mult-bit comparator implementation, the SNR increases by 6 dB for a 1 bit increase in the comparator resolution, which means that the 3 bit will have 12 dB increase in SNR while the 5 bit will have 24 dB increase in SNR as compared to the 1 bit implemnetation.
To debug the problem more, can you explain your simulation setup (Cadence/Matlab etc) in more detail?
A couple of questions to help in understanding your setup better :
i) Are you using ideal integrators/low pass filters in the loop filter?
ii) Are you implemneting multi-bit DAC correctly? Are you taking the FFT correctly for output of each of the three cases ( 1 bit, 3 bit and 5 bit outputs)?

Bharath
Hi Bharath,
Thanks for your reply.
I use active RC integrators to realize the loop filter, the amplifier used in the integrator is also realized by transistors. Its GWB is about 300MHz. The quantizer is a ideal one, described with verilog-a. For a 1bit quantizer the reference level is zero, and the coresponding output voltage is 1,-1. For 3 bit quantizer the reference level is 6/7, 4/7, 2/7, 0, -2/7, -4/7, -6/7 and the corresponding output voltage is 1, 5/7, 3/7, 1/7, -1/7, -3/7, -5/7, -1, respectively. For 5bits quantizer the reference level is 30/31,28/31...,0,...-28/31,-3/31 and the corresponding output voltage is 1, 29/31, 27/31, ..., ..., -29/31, -1, respectively. The output voltage of the quantizer is feedback through differente resistors connected to the inputs of the opamps.
Firstly, I simulate the modulator with a ideal clock, the SNR indeed increase about 12dB from 1bit quantizer to 3bit quantizer. But when i use clock with jitters, both modulator show a almost identical SNR.
sixth
The simulation tool is spectre and simulation result is sent to matlab to do FFT. For above 3 conditions, I use the same number of points (about 20000). For simplicity, the quantizer's output is recorded to do the FFT. In another words, the comparators and the DAC block is combined into a single block using verilog-a.
 

tsb_nph

Full Member level 2
Joined
Mar 9, 2005
Messages
125
Helped
23
Reputation
46
Reaction score
5
Trophy points
1,298
Location
USA
Activity points
2,820
Hi sixth,
The rule for increase in SNR ( 6 dB increase for every 1 bit increase in comparator resolution) is valid only when the in-band noise is limited by quantization noise (shaped by the high pass noise transfer function). But when the in-band noise is flat (white noise), then the rule is not valid.
Most probably, the in-band noise in the 3 bit and 5 bit case is white (jitter noise folds in band and becomes white noise), which limits the SNR.
To verify this, try decreasing the value of rms jitter ( say from 0.1% of clock cycle to 0.001% of the clock cycle). You should notice a change in SNR.

I don't have access to your Verilog-A model which combines both comparator and DAC, but the jitter should be modeled as variation in the DAC current/voltage pulse edges as it feeds back to the loop filter. Make sure this model is valid by checking the transient edges of the DAC pulses.
Another question is what kind of DAC pulse are you using - NRZ/RZ/HRZ? The shape of DAC pulse also changes the effect of clock jitter.

Hope this helps.

Bharath
 

    sixth

    Points: 2
    Helpful Answer Positive Rating

sixth

Member level 4
Joined
Feb 16, 2006
Messages
70
Helped
10
Reputation
20
Reaction score
0
Trophy points
1,286
Activity points
2,118
Hi,Bharath
From many papers I know that the continuous time sigma delta modulators with multi bit quantizer are not sensitive to the clock jitter. So, 5bit modulator should have better SNR performance than that of the 3bits and 1bit modulators, Is this right?
I have ask the question to Rechard Schreier. The following is the content of the email
cdy wrote:
> Dear Mr. Schreier:
> I am very sorry for bothering you but I do have a big and very
> strange trouble in designing the continuous time sigma delta modulator.
> Nobody can help me except you because you are the expert in sigma delta
> technique.
> I have designed 3 continuous time modulators and they have the same
> CIFB structure, the same coefficients (calculated using your matlab
> toolbox), I use the active RC integrator to realize the loop filter. The
> only difference between these 3 modulators is they have different
> quantizer levels, which is 1 bit, 3bits and 5bits respectively.
> With the ideal clock, which is 48MHz, I simulate these modulators
> and get 21600 points to do FFT(in matlab) for each modulator. The
> simulation results show that the SNR increases by about 12dB/2bits.It is
> reasonable.
> Then I add a 5ps rms jitter to the clock( using verilog-a) and
> simulate again (using spectre). The FFT results show that all these
> modulators have almost identical SNR!! From a lot of papers and theory,
> I knew that multibit quantizer is not sensitive to the clock jitter in
> continuous time sigma delta modulators. So, the modulator with 5bits
> quantizer would have better SNR performance than others. But my
> simulation shows that they are identical. I don't know why. I have asked
> many people and no results. Can you give me some advice about this
> strange question? If you are instested in this problem, I can give you
> more information about my design.
> Thank you very much!
>
> Best Regards!
> yours
> Dianyu Chen

With 5ps of jitter, the best SNR you can get is
OSR/(2*pi*f*sigma_t)^2, where f is the signal frequency
and sigma_t is the rms jitter. (Assuming white jitter.)
Once the modulator has enough quantizer bits to reach
this SNR value, adding more bits will not help. So,
I suspect that your 3-bit and 5-bit modulators have
reached this ceiling. It is surprising that your 1-bit
modulator has also reached this limit-- I can only assume
that you are using a fairly high test frequency.

Best of luck,
rs

--
Richard Schreier richard.schreier@analog.com
Analog Devices, Inc., Mail Stop 621 Tel: 781 937 2357
804 Woburn St, Wilmington MA 01887-3462 Fax: 781 937 1011
I think his answer is the same to yours. But I can't understand the formula in his email. It seems that the SNR does not dependent on the levels of the quantizers. That means that increase the levels of the quantizer has not any benefit to decrease the effect of the clock jitter at all, right?
sixth

Added after 5 hours 2 minutes:

The following figure is the FFT results of the modulator with 5bits quantizer
 

tsb_nph

Full Member level 2
Joined
Mar 9, 2005
Messages
125
Helped
23
Reputation
46
Reaction score
5
Trophy points
1,298
Location
USA
Activity points
2,820
sixth said:
Hi,Bharath
From many papers I know that the continuous time sigma delta modulators with multi bit quantizer are not sensitive to the clock jitter. So, 5bit modulator should have better SNR performance than that of the 3bits and 1bit modulators, Is this right?
I have ask the question to Rechard Schreier. The following is the content of the email

I think his answer is the same to yours. But I can't understand the formula in his email. It seems that the SNR does not dependent on the levels of the quantizers. That means that increase the levels of the quantizer has not any benefit to decrease the effect of the clock jitter at all, right?
sixth

Added after 5 hours 2 minutes:

The following figure is the FFT results of the modulator with 5bits quantizer
Hi sixth,
According to the formula in Dr Schreier's e-mail, SNR varies as

OSR/(2*pi*f*sigma_t)^2

Your statement that the SNR does not depend on the levels of quantizers is not correct. It actually is present in the aboveequation in a very subtle way.

Jitter power refers to the error voltage or current that is added/injected to the filter every cycle. Now, if you consider the error as the area under the rising or falling edges that have jitter (some shaded area that marks the jitter every cycle), you can see that area for a single code transition in a multi-bit case is far lower than the area for a single bit case. The area is in fact propotional to the quantization step, which is much lower for a five bit case, than for a single bit case. It is the difference in this area that manifests itself as the sigma_t. If the same clock jitter value is use din both cases, jitter power is lower because of the smaller quantization step size in a 5 bit case, as compared to the 1 bit case.
Is this explanation clear?

Regards,
Bharath
 

    sixth

    Points: 2
    Helpful Answer Positive Rating

sixth

Member level 4
Joined
Feb 16, 2006
Messages
70
Helped
10
Reputation
20
Reaction score
0
Trophy points
1,286
Activity points
2,118
Hi, Bharath
I have understood that formula from your explanation. Thank you very much!
But my simulation results does not obey that rule. For the same rms jitter, the SNR for a 5bits modulator should be better than that of the 3bits modulator. From the FFT result I can not see any benefit for multibit modulator in decreasing the jitter effect because they show identical SNR for for 1,3 and 5bits modulators. What I used in DAC is a NRZ pulse shape. The verilog-a model for quantizer&DAC is shown in the following list.
`include "discipline.h"
`include "constants.h"

module comparator (vin_p, vin_n, clk, voutp, voutn) ;
input vin_p, vin_n, clk;
output voutp, voutn;
electrical vin_p, vin_n, clk, voutp, voutn;
parameter real vrp15=30;
parameter real vrp14=28;
parameter real vrp13=26;
parameter real vrp12=24;
parameter real vrp11=22;
parameter real vrp10=20;
parameter real vrp9=18;
parameter real vrp8=16;
parameter real vrp7=14;
parameter real vrp6=12;
parameter real vrp5=10;
parameter real vrp4=8;
parameter real vrp3=6;
parameter real vrp2=4;
parameter real vrp1=2;
parameter real vrzo=0;
parameter real vrn1=2;
parameter real vrn2=4;
parameter real vrn3=6;
parameter real vrn4=8;
parameter real vrn5=10;
parameter real vrn6=12;
parameter real vrn7=14;
parameter real vrn8=16;
parameter real vrn9=18;
parameter real vrn10=20;
parameter real vrn11=22;
parameter real vrn12=24;
parameter real vrn13=26;
parameter real vrn14=28;
parameter real vrn15=30;

parameter real vda16p=15;
parameter real vda15p=13;
parameter real vda14p=11;
parameter real vda13p=9;
parameter real vda12p=7;
parameter real vda11p=5;
parameter real vda10p=3;
parameter real vda9p=1;
parameter real vda8p=15;
parameter real vda7p=13;
parameter real vda6p=11;
parameter real vda5p=9;
parameter real vda4p=7;
parameter real vda3p=5;
parameter real vda2p=3;
parameter real vda1p=1;
parameter real vda1n=-1;
parameter real vda2n=-3;
parameter real vda3n=-5;
parameter real vda4n=-7;
parameter real vda5n=-9;
parameter real vda6n=-11;
parameter real vda7n=-13;
parameter real vda8n=-15;
parameter real vda9n=-1;
parameter real vda10n=-3;
parameter real vda11n=-5;
parameter real vda12n=-7;
parameter real vda13n=-9;
parameter real vda14n=-11;
parameter real vda15n=-13;
parameter real vda16n=-15;
parameter real trans_clk=0;
parameter real tdel = 1p from (0:inf);
parameter real trise =1p from (0:inf);
parameter real tfal = 1p from (0:inf);

real vin,vop,von;

analog begin
@(initial_step("ac","dc","tran","xf")) begin
vop=0;
von=0;
end
vin=V(vin_p,vin_n);
@(cross(V(clk)-trans_clk,1)) begin
case (1)
(vin<=vrn15):begin vop=vda16n;von=vda16p;end
((vin>vrn15)&&(vin<=vrn14)):begin vop=vda15n;von=vda15p;end
((vin>vrn14)&&(vin<=vrn13)):begin vop=vda14n;von=vda14p;end
((vin>vrn13)&&(vin<=vrn12)):begin vop=vda13n;von=vda13p;end
((vin>vrn12)&&(vin<=vrn11)):begin vop=vda12n;von=vda12p;end
((vin>vrn11)&&(vin<=vrn10)):begin vop=vda11n;von=vda11p;end
((vin>vrn10)&&(vin<=vrn9)):begin vop=vda10n;von=vda10p;end
((vin>vrn9)&&(vin<=vrn8)):begin vop=vda9n;von=vda9p;end
((vin>vrn8)&&(vin<=vrn7)):begin vop=vda8n;von=vda8p;end
((vin>vrn7)&&(vin<=vrn6)):begin vop=vda7n;von=vda7p;end
((vin>vrn6)&&(vin<=vrn5)):begin vop=vda6n;von=vda6p;end
((vin>vrn5)&&(vin<=vrn4)):begin vop=vda5n;von=vda5p;end
((vin>vrn4)&&(vin<=vrn3)):begin vop=vda4n;von=vda4p;end
((vin>vrn3)&&(vin<=vrn2)):begin vop=vda3n;von=vda3p;end
((vin>vrn2)&&(vin<=vrn1)):begin vop=vda2n;von=vda2p;end
((vin>vrn1)&&(vin<=vrzo)):begin vop=vda1n;von=vda1p;end
((vin>vrzo)&&(vin<=vrp1)):begin vop=vda1p;von=vda1n;end
((vin>vrp1)&&(vin<=vrp2)):begin vop=vda2p;von=vda2n;end
((vin>vrp2)&&(vin<=vrp3)):begin vop=vda3p;von=vda3n;end
((vin>vrp3)&&(vin<=vrp4)):begin vop=vda4p;von=vda4n;end
((vin>vrp4)&&(vin<=vrp5)):begin vop=vda5p;von=vda5n;end
((vin>vrp5)&&(vin<=vrp6)):begin vop=vda6p;von=vda6n;end
((vin>vrp6)&&(vin<=vrp7)):begin vop=vda7p;von=vda7n;end
((vin>vrp7)&&(vin<=vrp8)):begin vop=vda8p;von=vda8n;end
((vin>vrp8)&&(vin<=vrp9)):begin vop=vda9p;von=vda9n;end
((vin>vrp9)&&(vin<=vrp10)):begin vop=vda10p;von=vda10n;end
((vin>vrp10)&&(vin<=vrp11)):begin vop=vda11p;von=vda11n;end
((vin>vrp11)&&(vin<=vrp12)):begin vop=vda12p;von=vda12n;end
((vin>vrp12)&&(vin<=vrp13)):begin vop=vda13p;von=vda13n;end
((vin>vrp13)&&(vin<=vrp14)):begin vop=vda14p;von=vda14n;end
((vin>vrp14)&&(vin<=vrp15)):begin vop=vda15p;von=vda15n;end
(vin>vrp15):begin vop=vda16p;von=vda16n;end
endcase
end
V(voutp) <+ transition(vop,tdel,trise,tfal);
V(voutn) <+ transition(von,tdel,trise,tfal);
end
endmodule
In the simulation, the reference levels and the corrsponding DAC output levels is set by parameters which i have listed in former posts.
Would you like to give me your personal email? Maybe we can discuss this problem in more detail. My email is cdy@mail.nankai.edu.cn.
Thank you any way.

sixth
 

currentmirror2000

Member level 4
Joined
Dec 21, 2004
Messages
77
Helped
6
Reputation
16
Reaction score
1
Trophy points
1,288
Activity points
798
hi guys,

can you also post your discussion result here? since i am very interesting in this topic; or would like to add me to your mailing list: currentmirror@gmail.com

btw, i don't understand why RZ has worse jitter performance compared to NRZ, say roughly around -6dB normally in terms of SNR.

thanks

c.m.
 

sixth

Member level 4
Joined
Feb 16, 2006
Messages
70
Helped
10
Reputation
20
Reaction score
0
Trophy points
1,286
Activity points
2,118
The following is the clock model
`include "constants.vams"
`include "disciplines.vams"

module ClockJitter(out);
output out;
electrical out;
parameter real freq=1 from (0:inf);
parameter real Vlo=-1,Vhi=1;
parameter real tt=0.01/freq from (0:inf);
parameter real td=3n from [0:inf);
parameter real jitter=0 from [0:0.1/freq);
integer n,seed;
real next,dT,vo;
analog begin
@(initial_step) begin
seed=286;
next=0.5/freq+$abstime;
end
@(timer(next))begin
n=!n;
dT=jitter*$dist_normal(seed,0,1);
next=next+0.5/freq+0.707*dT;
end
vo=n?Vhi:Vlo;
V(out)<+transition(vo,td,tt);
end
endmodule
I copy this model from Kunkert's paper. In fact I don't know if it is correct or not.
When I simulate this clock model, I found that the peak to peak jitter of the clock increase with the simulation time. When I set simulation time 10uS, the peak to peak jitter is about 100ps. if I change the time to 100us, the peak to peak jitter become 500ps, is it right? Moreover, the edge of the clock looks more like equal probability distribution than normal distribution. I obersve the clock jitter using the eye diagram.

sixth

Added after 9 minutes:

currentmirror2000 said:
hi guys,

can you also post your discussion result here? since i am very interesting in this topic; or would like to add me to your mailing list: currentmirror(at)gmail.com

btw, i don't understand why RZ has worse jitter performance compared to NRZ, say roughly around -6dB normally in terms of SNR.

thanks

c.m.

Hi,c.m.
In RZ pulse shape, the clock jitter affect both of the rising edge and the falling edge of the DAC feedback waveform while in NRZ pulse shape, only one edge will affect the performance. So its noise caused by jitter in RZ pulse shape will increase by double comparaing with NRZ form, that means 6dB.
 

currentmirror2000

Member level 4
Joined
Dec 21, 2004
Messages
77
Helped
6
Reputation
16
Reaction score
1
Trophy points
1,288
Activity points
798
hi sixth,

thank you for your reply! :D

in fact, i know NRZ has better jitter performance (in terms of SNR) than RZ and the 6dB is the conclusion from the paper you uploaded.

however, i feel the '6dB better' conclusion is not very accurate, becuase for NRZ the jitter is also dependent on the number of the transitions. please refer to the graph i attached: from clock cycle 2 to 3 and clock 6 to 7, there is no jitter associated with the NRZ!. but for NZ, no matter what the bit is, the jitter will always be associated in every half clock cycle. this is discussed in detail in cherry's book.

2ndly, the main problems make me confused, is how much 'worse' of the jitter effect on RZ than NRZ, or how to quantify the jitter effect in terms of SNR. by the way, to compare the jitter effect, one has to also take consideration of the fact that in each half cycle, the energy affected per edge of RZ is only 1/4 of than of NRZ: RZ=(±1-0)²=1 and NRZ=(1-(-1))² or (-1-1)²=4. in this sense, NRZ is infeiror than RZ (am i correct? :?:). again in cherry's book, NRZ will be 10log(2*N/Nt) dB in terms of SNR better than RZ, where N is the total bit number and Nt is the total transition. i just do not quite understand how this number comes out...


did i make myself clear on the question?

thank you!

c.m.
 

sixth

Member level 4
Joined
Feb 16, 2006
Messages
70
Helped
10
Reputation
20
Reaction score
0
Trophy points
1,286
Activity points
2,118
currentmirror2000 said:
hi sixth,

thank you for your reply! :D

in fact, i know NRZ has better jitter performance (in terms of SNR) than RZ and the 6dB is the conclusion from the paper you uploaded.

however, i feel the '6dB better' conclusion is not very accurate, becuase for NRZ the jitter is also dependent on the number of the transitions. please refer to the graph i attached: from clock cycle 2 to 3 and clock 6 to 7, there is no jitter associated with the NRZ!. but for NZ, no matter what the bit is, the jitter will always be associated in every half clock cycle. this is discussed in detail in cherry's book.

2ndly, the main problems make me confused, is how much 'worse' of the jitter effect on RZ than NRZ, or how to quantify the jitter effect in terms of SNR. by the way, to compare the jitter effect, one has to also take consideration of the fact that in each half cycle, the energy affected per edge of RZ is only 1/4 of than of NRZ: RZ=(±1-0)²=1 and NRZ=(1-(-1))² or (-1-1)²=4. in this sense, NRZ is infeiror than RZ (am i correct? :?:). again in cherry's book, NRZ will be 10log(2*N/Nt) dB in terms of SNR better than RZ, where N is the total bit number and Nt is the total transition. i just do not quite understand how this number comes out...


did i make myself clear on the question?

thank you!

c.m.
Hi,c.m.
You are right. the 6dB is a coarse estimation and I pick up this value because it is very easy to be understood.
For your question, I think there maybe something wrong. If you read Cherry's book carefully, you will find your answer. See Page114, "In an RZ modulator....."
Cherry uses a word "relative", I think its the critical point.
In another words, for the same structure, when we change NRZ waveform into RZ waveform, can you keep your coefficients unchange? If you use voltage feedback, the resistors must be reduced to half of its original value or the height of the feedback voltage must be increased to twice of its original value. If you use currren feedback, the current value must be double. That's all.
I hope this will help your.

sixth
 

currentmirror2000

Member level 4
Joined
Dec 21, 2004
Messages
77
Helped
6
Reputation
16
Reaction score
1
Trophy points
1,288
Activity points
798
sixth said:
Hi,c.m.
You are right. the 6dB is a coarse estimation and I pick up this value because it is very easy to be understood.
For your question, I think there maybe something wrong. If you read Cherry's book carefully, you will find your answer. See Page114, "In an RZ modulator....."
Cherry uses a word "relative", I think its the critical point.
In another words, for the same structure, when we change NRZ waveform into RZ waveform, can you keep your coefficients unchange? If you use voltage feedback, the resistors must be reduced to half of its original value or the height of the feedback voltage must be increased to twice of its original value. If you use currren feedback, the current value must be double. That's all.
I hope this will help your.

sixth

Hi sixth,

i understand what you mean about the coefficients scaling; but in the book pg114, it states:
'But now, energy is being transferred over only half a clock cycle; σβ is therefore twice as large relative to the energy transfer period in an RZ modulator'

to me, this is not related to the coefficients, but something about energy (or power?) transfer, which i do not quite understand. all these are used to calculate the effective value of σ²(δy).

btw, what's your way to simulate jitter? a time-varying jittered clock?

thanks,

c.m.
 

sixth

Member level 4
Joined
Feb 16, 2006
Messages
70
Helped
10
Reputation
20
Reaction score
0
Trophy points
1,286
Activity points
2,118
Hi sixth,

i understand what you mean about the coefficients scaling; but in the book pg114, it states:
'But now, energy is being transferred over only half a clock cycle; σβ is therefore twice as large relative to the energy transfer period in an RZ modulator'

to me, this is not related to the coefficients, but something about energy (or power?) transfer, which i do not quite understand. all these are used to calculate the effective value of σ²(δy).

btw, what's your way to simulate jitter? a time-varying jittered clock?

thanks,

c.m.

Hi,c.m.
'But now, energy is being transferred over only half a clock cycle; σβ is therefore twice as large relative to the energy transfer period in an RZ modulator'
the energy transfer in fact is the charge transfer, both voltage plus coefficients and current can be used to calculate the charge transferred. The charge transferred in RZ modulator must be identical with the charge transferred in NRZ form. I'm sorry i can't explain this problem cleary because english is not my nother language.
The verilog-a model used to describe the jitter has been posted in my form post.
sixth
 

sixth

Member level 4
Joined
Feb 16, 2006
Messages
70
Helped
10
Reputation
20
Reaction score
0
Trophy points
1,286
Activity points
2,118
I think I have found the answer about my question. The problem lies in the clock generator module, which is decribed by verilog-a. The jitter in which block is a FM jitter, which will be accumulated with the increase of the time. In fact, it is the accumulated jitter which limiter the modulator's performance.
The DAC block has also a minus problem, but not critical. If someone want to use it, please pay some attention to the reference level.
Thanks to Bharath and c.m.!
However, there rise a new question the clock jitter. Everyone who intersting in it can refer to the following link

We can discuss it in more detailed.

sixth
 

currentmirror2000

Member level 4
Joined
Dec 21, 2004
Messages
77
Helped
6
Reputation
16
Reaction score
1
Trophy points
1,288
Activity points
798
thank you very much for your sharing!!! it is indead very useful information to me!!!

i'll surely share my own issues if i encounter any.

c.m.
 

relqueseny

Newbie level 3
Joined
Apr 8, 2006
Messages
4
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,336
sixth said:
I think I have found the answer about my question. The problem lies in the clock generator module, which is decribed by verilog-a. The jitter in which block is a FM jitter, which will be accumulated with the increase of the time. In fact, it is the accumulated jitter which limiter the modulator's performance.
The DAC block has also a minus problem, but not critical. If someone want to use it, please pay some attention to the reference level.
Thanks to Bharath and c.m.!
However, there rise a new question the clock jitter. Everyone who intersting in it can refer to the following link
h**p://
We can discuss it in more detailed.

sixth


what do you mean by FM Jitter? , does this mean that the jitter has different types?
can you explain please

thanks in advance
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Top