rachee
Newbie
Hi, I'm a student and learning JasperGold. I have a question and be really grateful if you could help me.
I try to implement an assertion like this:
A |-> ##3 B;
In the main SystemVerilog module, I've defined A as an input and B as the output. I try to implement the code by using FSM. for example in one state, signal A should be high, then it counts 3 cycles through transferring to the next states, then it will check if B is high or not.
For the testbench, I found that JasperGold ignores initial blocks. So I can't use delays to write my testbench.
My question:
How can I write testbench for this, so my assertion would be passed?
signal A is high,
then I want to have signal B high, 3 cycles after signal A is high
I try to implement an assertion like this:
A |-> ##3 B;
In the main SystemVerilog module, I've defined A as an input and B as the output. I try to implement the code by using FSM. for example in one state, signal A should be high, then it counts 3 cycles through transferring to the next states, then it will check if B is high or not.
For the testbench, I found that JasperGold ignores initial blocks. So I can't use delays to write my testbench.
My question:
How can I write testbench for this, so my assertion would be passed?
signal A is high,
then I want to have signal B high, 3 cycles after signal A is high