Issues with my verilog code building this state diagram

[Verilognoob1]

Hello:

I'm having issues trying to build this state diagram into a Verilog code on ModelSim, my Verilog skills are very weak, thus I'm struggling with it.

The Problem:

Create Verilog source code that satisfies the given State Diagram. Prove, using a testbench, that your code satisfies every possible requirement

This is the state diagram


here is my attempt


main module

module HW11 (A, B, C, D, x, y, clock, reset);
  output reg  A, B, C, D;
  input x, y, clock, reset;
  
   reg [2:0] pstate, nstate;
  
  always @ (posedge clock or negedge reset)
    
      if (reset ==0) pstate <= A;
      else  pstate <= nstate;  
        
        
      
      always @ (pstate or x or y) begin
        
        case (pstate)
          A: if (x==0 && y==0) nstate <= A;
                  else if (x==0 && y==1) nstate <= B;
                  else if (x==1 && y==0) nstate <= C;
                  else nstate <= D;
          B: if (x==0 && y==0) nstate <= C;
                  else if (x==0 && y==1) nstate <= B;
                  else if (x==1 && y==0) nstate <= D;
                  else nstate <= A;
          C: if (x==0 && y==0) nstate <= D;
                  else if (x==0 && y==1) nstate <= B;
                  else if (x==1 && y==0) nstate <= C;
                  else nstate <= A;
          D: if (x==0 && y==0) nstate <= B;
                  else if (x==0 && y==1) nstate <= A;
                  else if (x==1 && y==0) nstate <= C;
                  else nstate <= D;
          endcase
        end
  
endmodule

and this is my testbench

module HW11_testbench;
wire A, B, C, D;
reg x, y, clock, reset;

HW11 I1 (A, B, C, D, x, y, clock, reset);
always
#10 clock = ~clock;
initial
begin
//$display ("time\t clock reset x y over under");
//$monitor ("%g\t %b\t %b\t %b\t %b\t %b\t %b", $time, clock, reset, x, y);

x = 0; y=0; clock = 1; reset = 0;
#5 reset = 1;
#10 reset = 0;
#10 x =0; y=0;
#10 x =0; y=1;
#10 x =1; y=0;
#10 x =1; y=1;
#10 x =0; y=0;
#10 x =0; y=1;
#10 x =1; y=0;
#10 x =1; y=1;

end
endmodule

and when I simulate it in ModelSim, I get unclear results, that I don't even know what I'm doing wrong... like I said, my Verilog skills are weak... I would appreciate any help, hints, ideas, and codes

Thanks in advance.

 

[FvM]

A-D are binary outputs but no legal values for the state variable. There's no connection between internal state and outputs A-D.

 

[Verilognoob1]

A-D are binary outputs but no legal values for the state variable. There's no connection between internal state and outputs A-D.

should I specifiy or make values for A-D ?
such as

parameter A = 2'b00;

 

[FvM]

Defining constant values for the states is a possible solution for the internal logic. But the outputs must get different names then.

 

[Verilognoob1]

Defining constant values for the states is a possible solution for the internal logic. But the outputs must get different names then.

would you please show me how it should be done? like I said I'm not that good with programming...

 

[FvM]

- The output names must be unique, different from other objects. E.g. Aout, Bout...

- You can assign the outputs to decoded states, e.g.

  assign Aout = (pstate == A);