Issues with loop stability of an LDO

[LvW]

Re: Loop stability

Can you also give an equivalent circuit of the loop structure, not considering transistors, just the gain blocks, respectively control process/controller. This would allow to assign the gain simulations and understand their meaning within the system.

As FvM has already proposed, it would be really helpful (more correct: necessary) to see a block diagram which represents your circuitry. This also would be of great value for you to understand the function of the circuit.
Only from such a block diagram you are able to decide which loop (if there are more than one) governs the behaviour of the whole system.

 

[ashish_chauhan]

Re: Loop stability

I did not get the mono load pulse ... do you mean a 0 to 5mA step or vice versa.

Is the lower loop stable? (I doubt)

for ur system to be stable both the loops have to be stable...

 

[LvW]

Re: Loop stability

for ur system to be stable both the loops have to be stable...

No, in general this is not a requirement since one loop can stabilize a second one.
Simple example: opamp with positive and negative feedback. If there is more negative than positive feedback the system is more stable.

 

[ashish_chauhan]

Re: Loop stability

what if its a loop in a loop...?
then both of them shud be stable... right?

 

[LvW]

Re: Loop stability

In this case: Yes, you are right.

 

[FvM]

Re: Loop stability

A block diagram had been given yesterday, without dimensioning, unfortunately. I don't really understand the motivation of the said feedforward path nor can I estimate it's behaviour due to missing gains and pole time constants.

Actually, there is some kind of underlying loop, cause the feedforward path is feeding the main path output signal backward to input, parasiticly through compensation network. But I don't expect that it plays an important role in instabilities.

 

[svraj]

Re: Loop stability

Hi,
I suggest that u run the two loops separately. Place only one iprobe at a time and run AC analysis in Spectre. Both must have stable phase margins in order for the entire system to be stable.

Rgds,
svraj

 

[safwatonline]

Loop stability

BTW the upper loop stability plot ( last plot u posted in 24 Jun 2008 19:34) is not stable !

 

[quaternion]

Re: Loop stability

I did not get the mono load pulse ... do you mean a 0 to 5mA step or vice versa.

It means {from 0--->0.5usec}current =0 , {from 0.5usec--->5.5usec}current =5mA , {from 5.5usec--->10usec}current =0 , and the transitions vary with 100psec rise and fall time.

Is the lower loop stable? (I doubt)

As it appears from the response of the lower loop its gain is lower than 0dB for all frequencies.

for ur system to be stable both the loops have to be stable...

the reason for using the lower loop is to stabilize the upper one .I don't know ,if the upper loop is stable why should I use the lower one.

I had replied to your PM ashish.

Actually, there is some kind of underlying loop, cause the feedforward path is feeding the main path output signal backward to input, parasiticly through compensation network. But I don't expect that it plays an important role in instabilities.

I dealt with the 3stage LDO as a 3 stage amplifier and makes a feedforward path across the first 2 stages and uses a cap across this feedfoward to control the generated zero , and the cap that connects its output to the output of the upper first 2 stages not to disturb the DC of the upper loop.

OK, here are other few comments:
1- try do stb analysis sweeping the load current (i.e. not just no load and full load but several steps), this to make sure that the PM is monotonic

You are right Safwat, when I made this I found that some values for current have phase resopnse for unstable system (this is unmonotonic change), although at full and no load the response is like as shown above (at first post)!!!!!!!!


Actually when I made the pole zero analysis , I get RHP copmplex poles !! , while all zeros in the LHP!! (varying the load current)


(note that maximum ωt I have is 20MHz )

 

[ashish_chauhan]

Re: Loop stability

safwatonline:

"BTW the upper loop stability plot ( last plot u posted in 24 Jun 2008 19:34) is not stable !"

very true...

"

 

[quaternion]

Re: Loop stability

I have a basic question , for compensation approaches other than pole splitting ones , What is the GBW ?
[for the pole splitting approaches the GBW = gm / Cm (transconductance at the device having the dominant pole per the compensation capacitance)]

 

[safwatonline]

Loop stability

gm/Cload (load compensated OTAs)

 

[quaternion]

Re: Loop stability

gm/Cload (load compensated OTAs)

Yes , and also in miller compensated 2stages and in all pole splitting compensated amplifiers (even advanced methods yield same GBW , such as automatic frequency compensation , and dual loop frequency compensation all has GBW = gm / Cm)

I mean ,is there is a compensation that yields a higher GBW?