issues faced at lower technology nodes

[aditya1579]

Hi,

A popular question asked in interviews is "what issues do you face while designing in lower technology nodes ?"

What should be a good answer to this ?

I feel issues like noise and congestion can be brought up. Could you please elaborate on this ?

Thanks,
Aditya

 

[saurabhr8here]

Here are a few, assuming that 'lower technology node' means FinFET based nodes (e.g. 14nm or below):
1. At sub-20nm nodes, min-pitch metals are printed using multiple-patterning (double or triple patterning), hence there are lots of restrictions on layout. Hence, achieving maximum density is difficult in multiple patterned technologies, drawn layouts can have 'coloring violations' which take a lot of time to resolve.
2. Multiple patterning has a lot of implications in routing layers (M2, M3, M4) and because of restrictive design rules, there is high probability of routing congestion when trying to achieve high utilizations in designs.
3. Because fins come at multiples of 1, getting arbitrary beta ratios in gates is not possible. Hence the different flavors of standard cells possible in planar technologies are not possible in FinFET technologies, which can degrade the final synthesized design. Basically, it is challenging to come up with an optimum standard cell library.
4. At scaled technologies, wire resistance increases a lot, especially because copper resistivity becomes orders of magnitude higher than bulk resistivity (scattering and grain boundary effects). This results in large number of buffer insertions for long wires, increasing power.
5. In addition to restrictive design rules, local interconnects are needed to contact the gate/source/drains of the transistors and additional VIA0 via are needed to contact up to M1. Hence, at a standard cell level, the amount of parasitic capacitance is very high. Hence the standard cells are heavily self-loaded, this degrades their ability to drive other gates/wires.