Issue with VHDL subtraction

Here is the issue with more details:
CounterA and CounterB are two integers configured to count different pulse widths .
I need to generate 2 pulse widths from A and B such that
result = CounterA + CounterB;
result1 = CounterA - CounterB;

The addition gives the correct result whereas the subtraction doesn't.
The subtraction works whenever CounterA > CounterB i.e ( result1 = CounterA - CounterB
However when CounterB > CounterA the result is always 0 instead of a negative number.
I have tried using signed variables too but it didnt work.
Can any1 let me know how to resolve this issue.

Please find below the code:

constant Count : integer := 255;
subtype Count_range is integer range 0 to Count ;
signal CounterA: Count_range ;
signal CounterB: Count_range ;
signal CounterAdd: Count_range;
signal CounterSubtract: Count_range;

CounterAdd <= ((CounterA) + ( CounterB));
CounterSubtract <= ((CounterA) - ( CounterB));

Hi,

You limit the value for CounterAdd and CounterSubtract to be between 0 and 255 (subtype Count_range). So you forbit negative values. You can also not get values above 255, eg. CounterA = 254 and CounterB = 4 does not work.

Devas

use normal integers 4 ur signals