# Issue with power estimation with PrimeTime

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#### asgirish13

##### Newbie level 1
Hello,

I am estimating the power consumed by my circuit post-synthesis and also post-layout using PrimeTime. I am facing a strange problem regarding the estimated power. The procedure that I follow is:

1. Get VCD file form Modelsim. I use the command “vcd add –r /cpu_test/cpu_inst/*” and run for about sometime.

2. Run the script in Primetime. The script that I use is:

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set power_enable_analysis true
set power_analysis_mode time_based
read_verilog ./netlists/cpu.v
current_design cpu
link_design
create_clock –period 40 –name clk clk
set_propagated_clock [all_clocks]
read_vcd –strip_path cpu_test/cpu_inst ./projects/project1/dump.vcd
read_sdf ./netlists/cpu.sdf
check_power
update_power
report_power

I get different power estimates for different duration of simulation on Modelsim for producing the VCD file. The figures varies from few microwatts to few kilowatts!!! Obviously this doesn’t make any sense. I observed that this difference is because of the power of 10 is different in each case. For e.g. once I get the power estimate as 1.771e-04, for another run I get as 0.0177 and yet another time I get 1.771e+3. This behaviour is same for both post-synthesis and post-layout simulations.

I can’t figure out the mistake that I am making. Can anybody please help?

Thanks in advance - Girish

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