Issue with modelling ADPLL in VHDL

[satishgra]

I am currently working on ADPLL modeling in VHDL. I am done with all the blocks except DCO.

Can somebody throw some light on exactly how we model DCO in VHDL. I had seen people using Look up tables which I feel is a pretty static approach.

Are there any others ways of doing it ?

Regards,
Satish

 

[FvM]

Are you talking about pure modelling or design for synthesis? For simulation purposes, you can use ieee.math_real, but if the simulation is related to hardware design, you would want to use the algorithm intended for hardware implementation, isn't it? So if the hardware uses a look-up table, the simulation would, too.

 

[satishgra]

Thanks for the reply... LUT is one way of implementing it
But, I am looking for a concrete approach. If i start with a schematic design, i will configure chain of inverters which would help me in generating different frequencies based on the control word.

But, I am just not able to think of something in that line.

 

[FvM]

Using a programmable ring oscillator is slightly different from the classical ADPLL approach, as introduced by Roland E. Best. See also the DIGICC PLL concept, patented by Cologne Chip: https://www.edaboard.com/threads/194547/

However, I dodn't exactly understand what's your problem in simulation.

 

[satishgra]

Hi,

I had worked on DPLL using spice. Now, I thought it was easy to model a ADPLL using the same knowledge.

I had successfully implemented all the other blocks. But, I understood that implementing a DCO using the ring oscillator methodology (set of inverter chains whose enable is controlled by the output of binary to thermometer decoder) is impossible in VHDL.

I did have a top level look at PLL book written by Roland. E Best.
I guess i might have to spend more time to really understand it. My Analog PLL knowledge does not seems to be sufficient to model the ADPLL


Regards,
Satish

 

[FvM]

But, I understood that implementing a DCO using the ring oscillator methodology (set of inverter chains whose enable is controlled by the output of binary to thermometer decoder) is impossible in VHDL.

Why a digital delay chain shouldn't be modelled by VHDL transport delay? Synthesis is a different thing. It has to refer to FPGA low level primitives as logic cells, or use synthesis attributes to enforce the implementation of logically redundant structures. The method should be discussed related to vendor libraries and tools, I suppose it's possible for any vendor somehow. Personally, I implemented delay chains with Altera FPGA, and there's a few Altera literature about it. Of course, if you have a synthesizable implementation, it could be also simulated at the gate level, but I think functional simulation with VHDL delays is easier (and faster anyway).