Issue with bootstrap sampling switch ?

[Electric_Shock]

**broken link removed**
**broken link removed**


I am designing a bootstrap sampling switch for ADC, but I have a problem that the voltage of Gate terminal of NMOS sampling switch is clipped when the vin is high. Vin is sine wave with amplitude of 1.8V, Vdd=1.8V, so the voltage Vg is idealy increase up to 3.6V when Vin=1.8V, but it is only 2.4V in practical. How do I solve this problem ? Thank you very much.

 

[d123]

Hi,

I'd show the actual circuit you are talking about and using. Meant helpfully, this is a: "I told the mechanic that my car doesn't work, it makes a funny noise, and I need it fixed but I won't take it to the workshop for him to look at..." thread .