Issue in pattern simulation

[vikas.m0502]

Hi,

While doing no-timing simulation I am getting X-0 mismatches.
I observed that the 'Clock' of the failing flops has a ‘x’ on the capture pulse, which is giving mismatch just before the next shift pulse.
Tracing it back leads to a clock gate, where the input clock is fine but output is going ‘x’ because of the Enable signal.
The enable is driven by 'sync' flop.
The SI of this sync flop is ‘x’. While tracing back, all flops in upstream have SI as ‘x’.
And no flop is getting forced in the test bench.

So, my query is that.
1) Is pattern needs to be re-generated here ?
2) If no, what may be the other possible reasons for x-propagation ?

Note: This is parallel scan test and I am using VCS for simulation.


Thanks,
Vikas

 

[maulin sheth]

Hello Vikas,

Actually for DFT purpose, Clock gating cell have two enable pins : One is used for test mode and second is used for functionally enable. So have you this type of cell?
While tracing back sync flop, why flop gives the X output. The same issue of clock gating cell to cells which you have traced back from sync flop? Whenever you traced back, first you just need to concentrate for clock, so what about the clock for other traced back cells? Is it correct or not?

Maulin

 

[rca]

1- the setup vector did a reset to clearly define all flip-flop elements?
2- ram/rom/flash/analog modules must have the behavior as the model, I means if during the ATPG the model indicate this output is =1, then the simulation model must have the same because the result will be different. One solution is to have black box for all of these module to be sure the patterns have been generated with "X" driven by these modules.
3- Normaly the unreset flip-flop should not made any simulation mistake, because during the first shift, the flip-flop will have a defined value. If you want to be sure the problem did not come from this un-reset flop, used a random tcl command to set at t=0.