I need to know the different isolation tech that can be done using the DNWELL , like Trench Isolation between RF chanel, or DNWELL under each RF channel .
I need to know the different isolation tech that can be done using the DNWELL , like Trench Isolation between RF chanel, or DNWELL under each RF channel .
In general you hav access to shallow trench, deep trench , deep Nwell and Nwell and P+ N+ diffs.
The deeper the barrier the better isolation. In fact the best would be if you would have EPI process with high resistive substrate. Then your Deep Nwell or deep trench would cut out the island on silicon so you would truly have a "separate" substrate for the given device. Since most of CMOS technologies do not provide high resistive substrate (quite often EPI and subst are about the same) those isolation techniques gives you some but not ideal isolation.
Deep Nwell to be really effective needs to have minimnm width == to EPI thickness.
To summarize - Deep trench #1, Deep Nwell #2 shallow trench #3
yes I hav access to shallow trench, deep trench , deep Nwell and Nwell and P+ N+ diffs
At first i make the isolation using deep trench (n+, OD, Nwell, and deep Nwell ), then more than one adv. me to use Deep nwell as it make it as island,
so which is better in isolation
Added after 14 minutes:
Teddy said:
Deep Nwell to be really effective needs to have minimnm width == to EPI thickness.
To summarize - Deep trench #1, Deep Nwell #2 shallow trench #3