ISE IPCore FIFO generator

[oboltys88]

Hello, when generating fifo with write_depth = 32 and wr_data_count and rd_data_count it is possible to write 31 bytes of data into fifo. When generating fifo with write_depth = 64 it is possible to write only 16 bytes of data into fifo. And data is written 1 time out 4 rising edges of clk. Anyone knows why is there such a feature of the fifo generator?

 

[TrickyDicky]

how wide is the data bus? a FIFO works as a first in first out - so the depth is just the max number of dwords you can input without reading any values before it is full. Otherwise you can put as many words in as you like.

 

[oboltys88]

how wide is the data bus? a FIFO works as a first in first out - so the depth is just the max number of dwords you can input without reading any values before it is full. Otherwise you can put as many words in as you like.

Databus is std_logic_vector (7:0). The problem is related to flags wr_data_count and rd_data_count. Without them it works fine.

 

[TrickyDicky]

what are the problems? the wr_data_count and rd_data count are just showing you how full the FIFO is. Is it a Dual clocked fifo? with dual clock the read side count will lag behind the write count by a few clocks.