ISCAS85 Spice Netlists

[dhaval4987]

Guys,

I need Spice netlists of ISCAS85 circuits. I have verilog files but to perform STA, I need Spice netlists. Is there a way I can get em? I am a student and dont have an access to a lot of tools.

If someone has any of such fancy tool please help me!

 

[phoenixpavan]

Maybe these threads might be of interest to you

https://www.edaboard.com/threads/55860/
https://www.edaboard.com/threads/16296/
https://www.edaboard.com/threads/14295/

 

[lostinxlation]

If the netlist is a cell based verilog, you must have .cdl for all the cells. Write a perl script to swap the verilog cell instances with the cell subckts from .cdl
It won't be very difficult. May be 100 lines or less is enough.

 

[dhaval4987]

Thanks Pavan,

But the problem is that
1. I am a student and dont have any of the tools mentioned in the links that you suggested.

2. I dont know Perl or Python.

is there any easy way out!?

 

[phoenixpavan]

Dhaval maybe I can point you to a thread with an example of how to use perl to convert

https://www.edaboard.com/threads/147765/

https://www.edaboard.com/threads/69520/#post849229

Learning perl is pretty easy just go through some links posted in the forum or from Web

About tools..maybe someone can give you pointers

cheers

 

[dhaval4987]

@All

Here is the useful link for the specified problem

Perform the SPICE Simulation of ISCAS85 Benchmark Circuits for research

I did upto the last stage and in the last stage - it shows some error! Still trying to figure out.

Let me know if someone can successfully run spicegen.pl without error.