Although identifiers in VHDL are not case-sensitive, the interpretation of enumeration literals such as 'Z' and 'L' is case-sensitive. This means that 'z' is not equivalent to 'Z'. VHDL for Programmable Logic - Kevin Skahill[/b]
If you are using Xilinx ise you can adjust the case sensitivity of the names. Juct click the process properties and you will see a case attribute. As default it says maintain you can also select upper lower cases. Hope it helps.
VHDL is not case sensitive. But 'X, 'Z' and others literals are defined using VHDL base types/primitives (even inside standard libraries). All this are not VHDL but defined using VHDL, and you need to use it exactly as defined (upper- or lower-case)
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VHDL is not case sensitive. Only exceptions are defined data types such as 'U', 'Z', 'X' ,etc. You should use uppercase for assigning these values to signals.
you are now modifying it with \....\. You can even use keywords inside it as the name of signals. I think we are not talking about such extended identifiers here.