Is VHDL capable of testing signal size?

[legendbb]

For example:

signal A : std_logic_vector(10 DOWNTO 0)

if sizeof(A) > 10 do ...
else do ...
end if;

???

Thanks, or use such condition in Generate clause?

 

[TrickyDicky]

yes you can. Arrays have attributes:

a_big_gen : if A'legnth > 10 generate...

etc.

 

[legendbb]

yes you can. Arrays have attributes:

a_big_gen : if A'legnth > 10 generate...

etc.

Thanks for quick answer!