Is this kind of code is one-hot coding style

[kurukuru]

code style one hot

Hi all,

I am a newbie in FPGA using VHDL language, I was told by my friend to try to write my code using state machine coz it easy to read and debug. I have coded my circuit as shown below and I’m wondering that whether this coding style called one-hot or not? (FYI, I have read many posts about one-hot coding theory but not quite understand how it looks like in VHDL code) Or if it not one-hot, how should I fix my code to be one-hot coding?

Thank you very much in advance

kurukuru

process (CLK, RST_L)
begin
	if (RST_L = '0') then
		wWR_EN <= '0';
		wWRITE_STATE <= WAIT_DATA;
	elsif (CLK'event and CLK = '1') then
		case wWRITE_STATE is
			when WAIT_DATA =>
				wWR_EN <= '0';
				if (wBYTE_COMPLETE = '1') then
					wWRITE_STATE <= START_WRITE;
				else
					wWRITE_STATE <= WAIT_DATA;
				end if;
			when START_WRITE =>
				wWR_EN <= '0';
				wWRITE_DATA <= wDATA_BUFFER (8 downto 1);
				wWRITE_STATE <= WRITING;
			when WRITING =>
				wWR_EN <= '1';
				wWRITE_STATE <= WAIT_DATA;
		end case;
	end if;
end process;

 

[shastri.vs]

fpga + one-hot code

I cant see where you re encoding the states.
You need assign values for the state register, otherwise you need to tell the synthesis tool which type of encoding you want , whether grey code or on hot etc.
If you are using ISE in synthesis report you can check the encoding method which the tool has used.

 

[kurukuru]

one hot fsm and grey code fsm

Thank you very much shastri.vs for your reply.

So you mean that my code is ready to be One-hot encoding. what I have to do is just select encoding style option in my synthesis program. Am I wrong?

By the way, I use Lattice FPGA and ispLever as a synthesis program. Then I found that there is [FSM Encoding = on (or off)] in properties of systhesis tools, does it refer to enable and disable one-hot encoding?

Thanks very much

 

[shastri.vs]

one hot coding refer

That doesnt mean it will do One-Hot encoding only. It may do any style. U can set it to One-Hot if they have given that option.
Otherwise u disable automatic encoding and do it manually in the code.
If there are 4 stages in ur FSM u need 4 bit state register to do one hot. U have to configure each register as follow.
reg1 <= "0001"
reg2 <= "0010"
reg3 <= "0100"
reg4 <= "1000"
Refer RTL Hardware Design using VHDl by Pong P Chu, it explains very clearly.

 

[kurukuru]

one hot coding

Thank you very much shastri.vs. I got it now