is this correct to use dummy poly for matching?

[zhangljz]

Hello,

I want to use dummy poly to improve layout matching. I use "poly_dg" layer to draw dummy poly. Is this a correct way to do it?

when I do LVS, there are warning "Missing connections stamping poly nodev by layer poly_cont".

While if I use "poly_dmy" layer, the DRC rule of "poly_dmy" is different . In PDK, it says "dummy poly rule is drawn dummy poly guideline purpose only, this rule is ignorable at designer's own risk".

Which should I follow?

Thanks

 

[erikl]

Which should I follow?

The "poly_dmy". They just want to tell you, that you are responsible that this is really a dummy.

 

[dick_freebird]

Dummy poly addresses gate litho loading but it does not
do anything for other effects like S/D (active) litho, STI
strain effects and so on. Best matching is always like-for-
like and that goes for dummies also (a dummy FET covers
all FET litho aspects, while selected FET-chunks do part
of the job).

Do you know that poly litho is the way-dominant factor?

Seems like one of the errors is whining about poly not
connected (floating poly)?

 

[zhangljz]

Hello erikl,

Thank you. I searched some threads and they said poly_dg and poly_dmy are the same material. So I can use either of them to draw dummy poly. Just poly_dg is mainly for transistor, but if I don't give it an active region, it is also a dummy poly.

The DRC difference between them I think may because poly_dmy is mainly used for automatic dummy filling. So a larger spacing of poly_dmy can reduce parasitic, and has less impact to the circuit

 

[erikl]

I think, for DRC the important difference is that the poly_dmy layer is a recognition layer for poly dummies, and so will be subject to relaxed connection rules. You might find out this by checking the DRC rules' file - if it isn't encrypted, or simply by trying both possibilities.