[SOLVED] is this code correct and what does this code do?

[Fractional-N]

is this VHDL code correct and what does this code do?

hi,
here is a VHDL code, can anyone explain it to me, please? i think it is somewhat strange and it could be written in only 3 line! (max) why there is more lines?

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Code VHDL - [expand]
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if (CLK' event and CLK = '1') then
    if ((DATA = '1') or (DATA_EN = '0')) then
        ID(7 downto 0)  <= DATA_IN;
        ID(15 downto 8) <= ID(7 downto 0);
        DATA_OUT        <= ID(15 downto 8);
    end if;

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[FvM]

It's syntactically correct and synthesizable VHDL. If it's correct in terms of the intended function can't be said without knowing the specification.

If you have problems to "see" the implemented function, draw the hardware. There are 3 8-bit registers with clock and clock enable.