Is there any timing done in early stages of design flow?

[vreddy]

Is there any timing done in early stages of design flow??
during floor & power planning??

according to my view there is no timing done at the early stage of the design but this was asked in one of the interview.....

help me out......

 

[straw]

timing

yes ,there have

 

[vreddy]

Re: timing

straw,

u said there is timing done in early stage of design during floorplan & powerplan can u elaborate it plz......

 

[shankarmit]

Re: timing

we will do prelayout STA analysis before starting the design.

 

[quan228228]

Re: timing

we also set timing constraint on design when synthesis.

The timing is the first thing to think about from chip definition, how fast your chip run. this is the most important performance of a chip.

The timing (clock) determines the usage of .13 tech or .09 tech or library etc.



quan228228

 

[eeeraghu]

Re: timing

Timing in early stages of design? with respect to what(compare) is it done?

 

[skymusic]

Re: timing

Compared to STA in synthesize, no more accurate parasitics can be extracted. The result of timing analysis in floorplan is similar to that in synthesize. STA is not need in stage of floorplan, except partition .

 

[pratap_v]

Re: timing

Yes, timing analysis is done before fp and placement. This is called as Zero RC in Encounter.
It actually does using only the cell delay information and not considering the net delays.