Guys,
I am in a phase of learning VHDL nowadays. I have a Verilog background. While going through the tools, it seems that some tools support VHDL-2008, which I think have a more compact syntax. Is there any way that whatever I am learning in VHDL is VHDL-2008? I mean I am new to the VHDL, so it will be better if I am directly learning 2008 version. Please post link or any other information here.
Most of the new features of VHDL 2008 only really apply to simulation and verification.
The features that do help for synthesis do help create some more compact code, but can all be done without it.
What the book doesnt cover is the fact VHDL 2008 allows packages as generics. This can be quite useful for verification, but currently not supported by anyone (Scheduled for ActiveHDL 10.6 ).