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Is there an IP core available in Xilinx software for VGA interface with FPGA.??

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dpaul

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In the spec above, look at the 3rd feature of this IP:
"Parameterizable TFT interface for 18-bit VGA or 24-bit DVI"

I think it is the only one provided by Xilinx.
 

shaiko

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VGA is an analog standard and requires a DAC for fully featured operation.
An FPGA is a digital device at heart.
Therefore, any implementation would have to be board specific...

It would be easier to search for such an IP through 3rd party companies that manufacture boards with Xilinx devices.

I'd try Digilent.com
 

Chethan Chethu

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thank you all.. bt i would like ask it more precisely now.. my doubt is dat " Do we have any option in Xilinx or Vivado to generate an VGA stand alone IP or can it be done by integrating other IP's like AXI n others.?? for example we create an DCM/ DDS/ ROM stand alone IP's.. Similarly for VGA.?
 

shaiko

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What FPGA are you using?
 

dpaul

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Try out the Xilinx XPS flow!
 

Chethan Chethu

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What FPGA are you using?

FPGA: Virtex-5 and 7.. i have both with me.. actually i have designed an DWT based OFDM system in Verilog using Xilinx14.4. Simulation results are coming from the system but have some problems in implementation i.e., VGA interface because my input is image data. Infact i have verified the output image in Matlab also. But for implementation i have less time, so thought of completing it using IP's.

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and i found this PDF( from the below link) for VGA interface. But i'm nt getting how to map/send my input image data to "LogiCORE IP AXI4-Stream to Video Out v2.01a" which is in hexa format(ROM).

https://www.xilinx.com/support/documentation/ip_documentation/v_axi4s_vid_out/v2_01_a/pg044_v_axis_vid_out.pdf[/PHP]



Kindly look into the Link and help me out...

- - - Updated - - -

Try out the Xilinx XPS flow!

and i found this PDF( from the below link) for VGA interface. But i'm nt getting how to map/send my input image data to "LogiCORE IP AXI4-Stream to Video Out v2.01a" which is in hexa format(ROM).

http://www.xilinx.com/support/docume...is_vid_out.pdf[/PHP]



Kindly look into the Link and help me out...
 

shaiko

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I might be wrong, but as far as I know Vivado support starts from series 7 FPGAs and above.
You'll have to use different environments for the 5 (ISE) and 7 (Vivado) devices.
 

dpaul

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I might be wrong, but as far as I know Vivado support starts from series 7 FPGAs and above.
You'll have to use different environments for the 5 (ISE) and 7 (Vivado) devices.
That's true, but still there a way to get the RTL of any Xilinx IP from the installation dir and then do manual RTL connection of the IP with the top level. ;-)

But I think the thread starter has a different problem. If I have understood him correctly....
He already has video data in some format and he wants to have a module in such a way that the module's o/p video data is in VGA format. Now this Xilinx IP we are talking about has data i/p in AXI format and o/p in VGA format. I have no experience in video signal processing or their formats so I might be wrong.
But in your design if you can somehow feed your video data in AXI format to this IP, then I guess your problem might be solved.

Some one with video signal processing experience might be able to guide you better.
 

Chethan Chethu

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That's true, but still there a way to get the RTL of any Xilinx IP from the installation dir and then do manual RTL connection of the IP with the top level. ;-)

But I think the thread starter has a different problem. If I have understood him correctly....
He already has video data in some format and he wants to have a module in such a way that the module's o/p video data is in VGA format. Now this Xilinx IP we are talking about has data i/p in AXI format and o/p in VGA format. I have no experience in video signal processing or their formats so I might be wrong.
But in your design if you can somehow feed your video data in AXI format to this IP, then I guess your problem might be solved.

Some one with video signal processing experience might be able to guide you better.

Yeh exactly dpaul i have input data in ROM which i need to send through AXI IP or any available IP and i need the output in VGA display.. But in dat IP there are many I/O signals.. dnw hw to send video data into AXI IP..

- - - Updated - - -

I might be wrong, but as far as I know Vivado support starts from series 7 FPGAs and above.
You'll have to use different environments for the 5 (ISE) and 7 (Vivado) devices.

Hi shaiko, we can use vivado even for 5series.. but 5 series FPGAs won't support most of the IP's especially AXI IP is nt thr for Virtex 5..
 

dpaul

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Yeh exactly dpaul i have input data in ROM which i need to send through AXI IP or any available IP and i need the output in VGA display.. But in dat IP there are many I/O signals.. dnw hw to send video data into AXI IP..

So this is the scenario...
You have a ROM and there are some signals/bus-system through which data can be transported out of the ROM. Now these o/p data format is not in AXI4. But the Xilinx IP you want to use has AXI4-Stream (data i/p) and AXI4-Lite (timing i/p) and VGA o/p.
If the above is true, then you need to build a protocol conversion bridge such that the bridge will convert you ROM signals to AXI format.

But in dat IP there are many I/O signals
I have seen only Pg8 of the spec. and there you have AXI4-Stream as video-data i/p signals and VGA as a o/p. There is also a AXI-4 Lite interface to which video-timing signals have to be fed.
Now as I have already mentioned I have no experience in video signal processing and so I don't know how exactly you have to partition your data coming out of the ROM to feed the AXI4-Stream as video data i/p and the AXI4-Lite as video timing input.
 
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Chethan Chethu

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So this is the scenario...
You have a ROM and there are some signals/bus-system through which data can be transported out of the ROM. Now these o/p data format is not in AXI4. But the Xilinx IP you want to use has AXI4-Stream (data i/p) and AXI4-Lite (timing i/p) and VGA o/p.
If the above is true, then you need to build a protocol conversion bridge such that the bridge will convert you ROM signals to AXI format.


I have seen only Pg8 of the spec. and there you have AXI4-Stream as video-data i/p signals and VGA as a o/p. There is also a AXI-4 Lite interface to which video-timing signals have to be fed.
Now as I have already mentioned I have no experience in video signal processing and so I don't know how exactly you have to partition your data coming out of the ROM to feed the AXI4-Stream as video data i/p and the AXI4-Lite as video timing input.

Thank you dpaul.. will find it out but i have another doubt regarding BER calculation. i know manual calculations and even through matlab/simulink.. but how to calculate using the formula BER= erfc(sqrt(Eb/No))..?? what is d errorfunction(erfc) in dat.? and confused with PSNR calculations as well.. can you temme bout this calculations plzz...
 

dpaul

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Sorry don't know about these stuff. Someone who has worked on vdo signal processing might be able to answer!
 

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