ajhunt18
Member level 1
Is there any component I could make use to replace the NMOS access transistors in the SRAM Cell? I am designing an SRAM using Verilog simulation.
Also, what possible techniques I could use to minimize the Leakage in the cell? Since I am using Latches, I am having hard time thinking of a leakage-minimizing technique. I am thinking of using NWL method, it's just that I am not certain about it's compatibility with the latches (cross-coupled inverters) in my SRAM cell.
Any help would be much appreciated. Thanks! :smile:
Also, what possible techniques I could use to minimize the Leakage in the cell? Since I am using Latches, I am having hard time thinking of a leakage-minimizing technique. I am thinking of using NWL method, it's just that I am not certain about it's compatibility with the latches (cross-coupled inverters) in my SRAM cell.
Any help would be much appreciated. Thanks! :smile:
