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Is that possible to synthesize mixed (vhdl & verilog) design using DC?

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kos8108

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Is that possible to synthesize mixed (vhdl & verilog) design using DC ?

Hello.
I'm currently working on a mixed design.

I'm going to finish verification until the simulation.

I'm trying to use DC for synthesis, but I don't feel it's a mixed design.

my design hierarchy is,
TB_TOP(verilog)
TOP(verilog)
1st_module(verilog)
sub_module(verilog)
2st_moudle(verilog)
sub_module(vhdl)
sub_module(verilog)
3st_moudle(verilog)
 

jbeniston

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Re: Is that possible to synthesize mixed (vhdl & verilog) design using DC ?

Yes, providing you have the require licenses.
 

ThisIsNotSam

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Re: Is that possible to synthesize mixed (vhdl & verilog) design using DC ?

Hello.
I'm currently working on a mixed design.

I'm going to finish verification until the simulation.

I'm trying to use DC for synthesis, but I don't feel it's a mixed design.

my design hierarchy is,
TB_TOP(verilog)
TOP(verilog)
1st_module(verilog)
sub_module(verilog)
2st_moudle(verilog)
sub_module(vhdl)
sub_module(verilog)
3st_moudle(verilog)

yes, it is.
 
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