Is system verilog the future??

[vivek]

verilog future

Hi
System verilog is now statndardized and has loads of industry support. Since it is a HDVL will SV proceeed to replace standard verilog/VHDL in design? Will SV slowly replace Vera and Specman/E as the language for verification? Please share your views on this..

Thanks
Vivek

 

[Nandy]

Verilog is so successful that a lot of companies have created their own efficient WRAP flow on it. Unless SV shows much stronger mulse, I don't see a big transition will happen in near future.

Nandy
www.nandigits.com
Netlist Debug/ECO in GUI mode.

 

[yeewang]

i agree with nandy.
i personally think systemC will have a brighter future for it has free simulation and a bunch of guys working on it in OSCI, it can be easily adopted by software engineers, it has good link between different abstraction levels and etc.

BTW, nandy, I tried your tool a little, is the GUI made by tk or sth.? I think it's a good start, but as a comercial eda, still way to go.

 

[nanako]

it really has to depend on how EDA vendor pushing for SystemVerilog. On specification alone systemverilog could replace vera, specman as the verification language but have all the EDA vendors implemented all those features is still another question.

 

[Nandy]

Hi Yeewang

Thank you for using GOF. I am still adding more and more features. And tunning up GUI interface which is in Tk. I would appericiate if you point out any improvements.

Thanks.

Nandy
www.nandigits.com
Netlist Debug/ECO in GUI mode.

 

[xworld2008]

I think system verilog better than vera , e in verification, becase vera , e is a co-simulation, and now cadence have soft to supply system verilog

 

[bansalr]

system verilog is definately going to be ahead in verification domain. It also depends upon the EDA vendors support. Since people are comfortable with verilog so system Veilog will definately have and edge over propritery language like e.

But we cannot compare it with SystemC . since systemC will explore totally a new
domain which is ESL.and systemC will have more advantage in exploring the executibale specification modelling and bit on verification too.

As i have done survey on the ESL tools . Almost all the industry ESL tools support systemC in one way or other.

 

[aji_vlsi]

Verilog is so successful that a lot of companies have created their own efficient WRAP flow on it. Unless SV shows much stronger mulse, I don't see a big transition will happen in near future.

Nandy
www.nandigits.com
Netlist Debug/ECO in GUI mode.

Hi,
As many of you might know, SV is 100% backward compatible with Verilog, hence no fear of "throwing away" old flow(s). SV does have compelling features/constructs - such as SVA, SV-Testbench to name a few. So I do see an evolutinary adoption of SV. It will not be a revolution such as the one with Vera/E though.

Regards
Ajeetha
www.noveldv.com

 

[nagraj]

Verilog is so successful that a lot of companies have created their own efficient WRAP flow on it. Unless SV shows much stronger mulse, I don't see a big transition will happen in near future.

Nandy
www.nandigits.com
Netlist Debug/ECO in GUI mode.

Hi,
As many of you might know, SV is 100% backward compatible with Verilog, hence no fear of "throwing away" old flow(s). SV does have compelling features/constructs - such as SVA, SV-Testbench to name a few. So I do see an evolutinary adoption of SV. It will not be a revolution such as the one with Vera/E though.

Regards
Ajeetha
www.noveldv.com

I am caught up with question.
How do one will replace existing e code with adoption from SV ? This competition b/w different vendors is leading to orthodox platforms where multiple language support will become a factor in integrating different existing test benches.

 

[vizpal]

Many companies have started shifting to SV. One good reason is that -> supports DESIGN and VERIFICATION . But it would take a very very long time to stabilize...:!:
Who knows , what if some thing better comes up in between???

 

[sanjay11]

system verilog is good but can't replace 'e' as it is more advanced, powerful.
but it is free.

 

[modelsim62c]

system verilog is good but can't replace 'e' as it is more advanced, powerful.
but it is free.

'e' is not free, and only one vendor (Cadence) really supports it.

What areas is 'E' better? I'm curious, since I know Systemverilog tries to do everything (RTL-constructs, testbench costurcts, assertions, OOP testbench). It doesn't surprise me Systemverilog sacrificed some specialized capability for more generality.

 

[vikas_lakhanpal27]

No one can predict anyones future!
Lets see wat happens..

 

[moorhuhn]

System Verilog IS in my opinion already now Nr.1. It is sw vendor independent and thus sw vendors are very motivated to offer bunch of helpful libs for free.
(See AVM from Mentor - supported SV and SystemC, recently OVM from Mentor and Cadence - supporting just SV(!))

I would not recommend to start with SV from scratch without reusing any lib. This is not like Verilog or VHDL you could simply start to play with and get reasonable results in reasonable time frame.