We often see AHB or APB in SOC system using ARM CPU and other bus such WISHBONE is also used in some 32-bit CPU system.
But in my design case,a 8-bit CPU(ex.8051) is enough to read/write the 8-bit control/status registers in the co-processors(maybe 3 or 4).And i want to make the co-processors access the data in the RAM directly,which is to be processed.So i am trying to design a bus to connect the CPU,the processors ,and an arbiter is also needed.But i can hardly find a 8-bit bus design in the papers.So i want to know whether my design is realizable and resonable or not? Thanks!
As an alternative,I can connected all the control/status registers and RAM to the 8-bit CPU and map them as outside RAM.But the CPU will take over all the data transfers,which takes more time compared to using a bus.
if the processor will not connect other device designed by others, you can use any bus, of course the data is 8 bits, even you can define a bus by yourself
As u r planning for an soc, u can define a ur own particular bus which suits all ur devices, i.e 8 bitdata bus and supports 2 or 3 masters and an arbiter for these masters.
Even though u use AHB bus u can use only 8-bit bus, There are four strobes for example for a 32 bit bus i.e
0-7 bits, 0001
8-15 bits, 0010
16-23 bits, 0100
24-31 bits,1000
if u use 1111 then the data is 32 bits
and also u can use HBurst and HSize in the AHB protocol