Is POWER Compiler needed?

[cnspy]

In my design. Most modules have gated-clock design, do you think the POWER Compiler is needed for my design to save power?



Thanks in advance.

 

[wadaye]

Hi cnspy:

Power Compiler not only means gated clock, you can use it for some

other useage to save power. You can use power compiler to do RTL

power estimation, Gate level power analysis and optimization, Leakage

Power optimization.

wang1

 

[eda_wiz]

In my design. Most modules have gated-clock design, do you think the POWER Compiler is needed for my design to save power?

Thanks in advance.

if u have gated clock in your design U better use power compiler .. since it automatically selects latch based clock gate circuitry during synthesis . Also optimises power as wadaye said...

Well mr wadaye .. I have a doubt regarding power estimation.. the power reported by power compiler depends on the test patter and simulation time.. the power calculated from a netlist toggle report by simulating for 2 different timedurations will be different.. in that case how will you say my RTL consumes this much power???

 

[cnspy]

In my library, it has the GATED_CLK cell. DC has Multi-Vt features. We have use it.

I am not sure what will power compiler do for the NETLIST optimization

 

[heartfree]

yes, as you said, in multi-vt env, power compiler can change low vt cell to high vt cell for better leakage power. Anyway, it will not affect your timing .

 

[heartfree]

In my design. Most modules have gated-clock design, do you think the POWER Compiler is needed for my design to save power?

Thanks in advance.

if u have gated clock in your design U better use power compiler .. since it automatically selects latch based clock gate circuitry during synthesis . Also optimises power as wadaye said...

Well mr wadaye .. I have a doubt regarding power estimation.. the power reported by power compiler depends on the test patter and simulation time.. the power calculated from a netlist toggle report by simulating for 2 different timedurations will be different.. in that case how will you say my RTL consumes this much power???

Dynamic power consumption surely depend on different test patter, which will generate different switching activity. but for Leakage power consumption, it is decided by standcell itself.

 

[visualart]

I think u need design all clock in only one clock,
the clock in the other module comes from it, and one module only one clock