is post layout simulation obligatory?

[memsgg]

Hi,

I design an ic using an opamp cell from CDK, but the CDK can not do the post layout simulation including the opamp cell, my quetion is:

1. I don't want to design the opamp by myself, is there any problems for using the opamp cell from CDK?

2. what is the postlayout mainly for? I think it is for paracitics capacitor and resistor, is it right?

3. the working frequency is less than 10kHz, must I do the post layout simulation before tapeout?

Thanks in advance
Yong

 

[MSSN]

2. what is the postlayout mainly for? I think it is for paracitics capacitor and resistor, is it right?

3. the working frequency is less than 10kHz, must I do the post layout simulation before tapeout?

Yes, post layout is mainly for parasitic capacitors and resistors.
It's not a must , however it is risky to tapeout without post layout simulation, however u can add parasitic capacitors and resistors at the sensitive nodes in ur circuit to check the affect of layout parasitics on ur design but this also doesn't guarantee that u have taken all the layout effects in ur consideration.

 

[memsgg]

I don't know how to do now, the Design kit uses dracula to erc and lvs, but doesn't support the post layout simulation if I use their opamp cells. is it strange?

And I think 10kHz is low, and the parasitic capacitor should be ok, is it right?

Can anyone help me?

Thanks a lot

 

[acbalbason]

hi!

i tried post layout simulation but only after i designed the op amp itself. i instanced my own design after parasitic rc extraction. haven't tried simulating the available op amp included in the kit.

try designing one?

- al

 

[memsgg]

2. what is the postlayout mainly for? I think it is for paracitics capacitor and resistor, is it right?

3. the working frequency is less than 10kHz, must I do the post layout simulation before tapeout?

Yes, post layout is mainly for parasitic capacitors and resistors.
It's not a must , however it is risky to tapeout without post layout simulation, however u can add parasitic capacitors and resistors at the sensitive nodes in ur circuit to check the affect of layout parasitics on ur design but this also doesn't guarantee that u have taken all the layout effects in ur consideration.

But I think the frequency is very low, 10KHz, so it is unnecessary to do the postlayout simulation, is it right?